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SI3232
D U A L PR O G R A M M A B L E C M O S S L I C W I T H L I N E M O N I T O R I N G
Features
Ideal for customer premise applications Low standby power consumption: <65 mW per channel Internal balanced ringing to 65 Vrms Software programmable parameters: Ringing frequency, amplitude, cadence, and waveshape Two-wire ac impedance DC loop feed (18-45 mA) Loop closure and ring trip thresholds Ground key detect threshold Automatic switching of up to three battery supplies On-hook transmission Loop or ground start operation with smooth/abrupt polarity reversal SPI bus digital interface with programmable interrupts 3.3 V operation GR-909 loop diagnostics and loopback testing 12 kHz/16 kHz pulse metering Lead-free/RoHS compatible packages available
Ordering Information See page 122. U.S. Patent #6,567,521
Applications
Cable telephony Wireless local loop Voice over IP/voice over DSL ISDN terminal adapters
U.S. Patent #6,812,744 Other patents pending
Description
The SI3232 is a low-voltage CMOS SLIC that offers a low-cost, fully softwareprogrammable, dual-channel, analog telephone interface for customer premise (CPE) applications. Internal ringing generation eliminates centralized ringers and ringing relays, and on-chip subscriber loop testing allows remote line card and loop diagnostics with no external test equipment or relays. The SI3232 performs all programmable SLIC functions in compliance with all relevant LSSGR, ITU, and ETSI specifications; all high-voltage functions are performed by the Si3200 linefeed interface IC. The SI3232 operates from a single 3.3 V supply and interfaces to a standard SPI bus digital interface for control. The Si3200 operates from a 3.3 V supply as well as high-voltage battery supplies up to 100 V. The SI3232 is available in a 64-pin thin quad flat package (TQFP), and the Si3200 is available in a thermally-enhanced 16-pin small-outline (SOIC) package.
Functional Block Diagram
INT RESET
CS SCLK SDI SDO VRXPa VRXNa VTXPa VTXNa VTXPb VTXNb VRXPb VRXNb VCM PCLK
SI3232
Ring Source
Linefeed & Monitor
SPI Control Interface
Si3200 Linefeed Interface
TIP RING
Ring Source
Linefeed & Monitor
Si3200 Linefeed Interface
TIP RING
PLL
FSYNC
Preliminary Rev. 0.96 2/05
Copyright (c) 2005 by Silicon Laboratories
SI3232
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
SI3232
2
Preliminary Rev. 0.96
SI3232 TABLE O F CONTENTS
Section Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3. Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.1. Linefeed Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2. Power Supply Transients on the Si3200 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.3. DC Feed Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.4. Linefeed Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.5. Automatic Dual Battery Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.6. Ringing Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.7. Internal Unbalanced Ringing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 4.8. Ring Trip Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.9. Ring Trip Timeout Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.10. Ring Trip Debounce Interval . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 4.11. Loop Closure Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 4.12. Relay Driver Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 4.13. Two-Wire Impedance Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 4.14. Audio Path Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 4.15. System Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4.16. SPI Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 4.17. SI3232 RAM and Register Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 4.18. System Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 5. 8-Bit Control Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 6. 8-Bit Control Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 7. 16-Bit RAM Address Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 8. 16-Bit Control Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 9. Pin Descriptions: SI3232 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 10. Pin Descriptions: Si3200 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120 11. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 12. Product Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122 12.1. Part Designators (Partial List) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 13. Package Outline: 64-Pin eTQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 14. Package Outline: 16-Pin ESOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Support Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
Preliminary Rev. 0.96
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SI3232
1. Electrical Specifications
Table 1. Absolute Maximum Ratings and Thermal Information1
Parameter Supply Voltage, Si3200 and SI3232 High Battery Supply Voltage2 Si32002 Symbol
VDD, VDD1-VDD4 VBATH
Test Condition Continuous 10 ms Continuous Continuous Pulse < 10 s Pulse < 4 s
Value -0.5 to 6.0 0.4 to -104 0.4 to -109 VBATH -104 VBATH -15 VBATH -35 100 20
Unit V V V V V V mA mA mA V C C C/W C/W W W
Low Battery Supply Voltage, TIP or RING Voltage, Si3200
VBAT, VBATL VTIP, VRING
TIP, RING Current, Si3200 STIPAC, STIPDC, SRINGAC, SRINGDC Current, SI3232 Input Current, Digital Input Pins Digital Input Voltage Operating Temperature Range Storage Temperature Range SI3232 Thermal Resistance, Typical3 (TQFP-64 ePad) Si3200 Thermal Resistance, Typical3 (SOIC-16 ePad) Continuous Power Dissipation, Si32004 Continuous Power Dissipation, SI3232
ITIP, IRING
IIN VIND TA TSTG JA JA PD PD
Continuous
10 -0.3 to (VDD + 0.3) -40 to 100 -40 to 150 25 55
TA = 85 C, SOIC-16 TA = 85 C, TQFP-64
1 1.6
Notes: 1. Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. The dv/dt of the voltage applied to the VBAT, VBATH, and VBATL pins must be limited to 10 V/s. 3. The thermal resistance of an exposed pad package is assured when the recommended PCB layout guidelines are followed correctly. The specified performance requires that the exposed pad be soldered to an exposed copper surface of equal size and that multiple vias are added to enable heat transfer between the top-side copper surface and a large internal copper ground plane. Refer to "AN55: Dual ProSLICTM User Guide" or to the SI3232 evaluation board data sheet for specific layout examples. 4. On-chip thermal limiting circuitry will shut down the circuit at a junction temperature of approximately 150 C. For optimal reliability, operation above 140 C junction temperature should be avoided.
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SI3232
Table 2. Recommended Operating Conditions
Parameter Ambient Temperature Ambient Temperature SI3232 Supply Voltage Si3200 Supply Voltage High Battery Supply Voltage, Si3200 Low Battery Supply Voltage, Si3200 Symbol TA TA VDD1-VDD4 VDD
VBATH VBATL
Test Condition K-grade B-grade
Min* 0 -40 3.13 3.13 -15 -15
Typ 25 25 3.3 3.3 -- --
Max* 70 85 3.47 3.47 -99
VBATH
Unit
o
C
oC
V V V V
*Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 oC unless otherwise stated.
Preliminary Rev. 0.96
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SI3232
Table 3. Power Supply Characteristics1
(VDD, VDD1-VDD4 = 3.3 V, TA = 0 to 70 C for K-Grade, -40 to 85 C for B-Grade)
Parameter VDD1-VDD4 Supply Current (SI3232)
Symbol IVDD1-IVDD4
Test Condition Sleep mode, RESET = 0 Open (high impedance) Active on-hook standby Forward/reverse active off-hook ABIAS = 4 mA Forward/reverse active OHT OBIAS = 4 mA Ringing, VRING = 45 Vrms, VBAT = -70 V, Sine Wave, 1 REN load2
Min -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Typ 1 15 15 20 12 + ILIM 28 100 100 110 110 110 110 100 225 400 4.4 + ILIM 8.4 6
Max -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Unit mA mA mA mA mA mA A A A A A A A A A mA mA mA
VDD Supply Current (Si3200)
IVDD
Sleep mode, RESET = 0 Open (high impedance) Active on-hook standby Forward/reverse active off-hook, ABIAS = 4 mA, VBAT = -24 V Forward/reverse OHT, OBIAS = 4 mA, VBAT = -70 V Ringing, VRING = 45 Vrms, VBAT = -70 V, Sine Wave, 7 REN load
VBAT Supply Current (Si3200)
IVBAT
Sleep mode, RESET = 0, VBAT = -70 V Open (high impedance), VBAT = -70 V Active on-hook standby, VBAT = -70 V Forward/reverse active off-hook, ABIAS = 4 mA, VBAT = -24 V Forward/reverse OHT, OBIAS = 4 mA, VBAT = -70 V Ringing, VRING = 45 Vrms, VBAT = -70 V, Sine wave, 1 REN load2
Notes: 1. All specifications are for a single channel based on measurements with both channels in the same operating state. 2. See "4.7.4. Ringing Power Considerations" for current and power consumption under other operating conditions. 3. Power consumption does not include additional power required for dc loop feed. Total system power consumption must include an additional VBAT x ILIM term.
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SI3232
Table 3. Power Supply Characteristics1 (Continued)
(VDD, VDD1-VDD4 = 3.3 V, TA = 0 to 70 C for K-Grade, -40 to 85 C for B-Grade)
Parameter Power Consumption
Symbol PSLEEP POPEN PSTBY PSTBY PACTIVE3 PACTIVE3 POHT POHT PRING
Test Condition Sleep mode, RESET = 0, VBAT = -70 V Open (high impedance), VBAT = -70 V Active on-hook standby, VBAT = -48 V Active on-hook standby, VBAT = -70 V Forward/reverse active off-hook, ABIAS = 4 mA, VBAT = -24 V Forward/reverse active off-hook, ABIAS = 4 mA, VBAT = -48 V Forward/reverse OHT, OBIAS = 4 mA, VBAT = -48 V Forward/reverse OHT, OBIAS = 4 mA, VBAT = -70 V Ringing, VRING = 45 Vrms, VBAT = -70 V, Sine Wave, 1 REN load2
Min -- -- -- -- -- -- -- -- --
Typ 8 65 70 80 175 280 500 685 516
Max -- -- -- -- -- -- -- -- --
Unit mW mW mW mW mW mW mW mW mW
Notes: 1. All specifications are for a single channel based on measurements with both channels in the same operating state. 2. See "4.7.4. Ringing Power Considerations" for current and power consumption under other operating conditions. 3. Power consumption does not include additional power required for dc loop feed. Total system power consumption must include an additional VBAT x ILIM term.
Preliminary Rev. 0.96
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SI3232
Table 4. AC Characteristics
(VDD, VDD1-VDD4 = 3.13 to 3.47 V, TA = 0 to 70 C for K-Grade, -40 to 85 C for B-Grade)
Parameter TX Full Scale Output RX Full Scale Input
Test Condition TX/RX Performance VTXP-XTXN VRXP-VRXN, ARX = 0 dB ARX = -3.52 dB ARX = -6.02 dB CMTXSEL = 1 CMTXSEL = 0 ATX stage = 0 dB, THD = 1.5%
1
Min 0.1 0.25 0 0 0.6 -- 2.5 Figure 4 -- -- -- --
Typ -- -- -- -- -- 1.5 -- -- -74 -74 -74 -- -- --
Max VDD-0.1 VDD-0.25 VDD VDD 1.5 -- -- -- -68 -65 -68 -41 +0.25 10
Unit V V V V V V VPK dB dB
Analog Input/Output Common Mode Voltage Overload Level Overload Compression Single Frequency Distortion
2-wire to 4-wire or 4-wire to 2-wire: 200 Hz-3.4 kHz 2-wire to 4-wire to 2-wire: 200 Hz-3.4 kHz
Signal-to-(Noise + Distortion) Ratio2 Intermodulation Distortion Gain Accuracy2 Gain Distortion vs. Frequency Gain Tracking
200 Hz-3.4 kHz Active off-hook, and OHT, any ZT 2-Wire to 4-Wire or 4-Wire to 2-Wire, 1014 Hz, Any gain setting -3 dB corners 1014 Hz sine wave, reference level -10 dBm signal level: 3 dB to -37 dB -37 dB to -50 dB -50 dB to -60 dB 0 dBm0, 300 Hz to 3.4 kHz 300 Hz to 3.4 kHz 200 Hz to 3.4 kHz
dB dB kHz
-0.25 0.01
-- -- -- -- -- 26
-- -- -- -- -- 30
0.25 0.5 1.0 -75 -75 --
dB dB dB dB dB dB
Crosstalk between channels TX or RX to TX TX to RX to RX 2-Wire Return Loss3
Notes: 1. The input signal level should be 0 dBm0 for frequencies greater than 100 Hz. For 100 Hz and below, the level should be -10 dBm0. The output signal magnitude at any other frequency will be smaller than the maximum value specified. 2. Analog signal measured as VTIP - VRING. Assumes ideal line impedance matching. 3. VDD = 3.3 V, VBAT = -52 V, no fuse resistors, RL = 600 , ZS = 600 synthesized using RS register coefficients. 4. The level of any unwanted tones within the bandwidth of 0 to 4 kHz will not exceed -55 dBm. 5. The OBIAS and ABIAS registers program the dc bias current through the SLIC in the on-hook transmission and offhook active conditions, respectively. This per-pin total current setting should be selected such that it can accommodate the sum of the metallic and longitudinal currents through each of the TIP and RING leads for a given application.
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Preliminary Rev. 0.96
SI3232
Table 4. AC Characteristics (Continued)
(VDD, VDD1-VDD4 = 3.13 to 3.47 V, TA = 0 to 70 C for K-Grade, -40 to 85 C for B-Grade)
Parameter Idle Channel Noise4
Test Condition Noise Performance C-Message weighted Psophometric weighted 3 kHz flat
Min -- -- -- 40 60 58 53 40
Typ 12 -78 -- -- -- 63 58 --
Max 15 -75 18 -- -- -- -- --
Unit dBrnC dBmP dBrn dB dB dB dB dB
PSRR from VDD1 - VDD4 PSRR from VBAT Longitudinal to Metallic Balance (forward or reverse) Metallic to Longitudinal Balance Longitudinal Impedance5
RX and TX, dc to 3.4 kHz RX and TX, dc to 3.4 kHz Longitudinal Performance 200 Hz to 1 kHz 1 kHz to 3.4 kHz 200 Hz to 3.4 kHz 200 Hz to 3.4 kHz at TIP or RING Register-dependent
OBIAS/ABIAS
00 = 4 mA 01 = 8 mA 10 = 12 mA 11 = 16 mA Longitudinal Current per Pin5 Active off-hook 200 Hz to 3.4 kHz Register-dependent
OBIAS/ABIAS
-- -- -- --
50 25 25 20
-- -- -- --

00 = 4 mA 01 = 8 mA 10 = 12 mA 11 = 16 mA
-- -- -- --
4 8 8 10
-- -- -- --
mA mA mA mA
Notes: 1. The input signal level should be 0 dBm0 for frequencies greater than 100 Hz. For 100 Hz and below, the level should be -10 dBm0. The output signal magnitude at any other frequency will be smaller than the maximum value specified. 2. Analog signal measured as VTIP - VRING. Assumes ideal line impedance matching. 3. VDD = 3.3 V, VBAT = -52 V, no fuse resistors, RL = 600 , ZS = 600 synthesized using RS register coefficients. 4. The level of any unwanted tones within the bandwidth of 0 to 4 kHz will not exceed -55 dBm. 5. The OBIAS and ABIAS registers program the dc bias current through the SLIC in the on-hook transmission and offhook active conditions, respectively. This per-pin total current setting should be selected such that it can accommodate the sum of the metallic and longitudinal currents through each of the TIP and RING leads for a given application.
Preliminary Rev. 0.96
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SI3232
Table 5. Linefeed Characteristics
(VDD, VDD1-VDD4 = 3.13 to 3.47 V, TA = 0 to 70 C for K-Grade, -40 to 85 C for B-Grade)
Parameter DC Loop Current Accuracy DC Open Circuit Voltage Accuracy DC Differential Output Resistance DC On-Hook Voltage Accuracy--Ground Start DC Output Resistance-- Ground Start DC Output Resistance-- Ground Start Loop Closure Detect Threshold Accuracy Ground Key Detect Threshold Accuracy Ring Trip Threshold Accuracy
Symbol
Test Condition ILIM = 18 mA Active Mode; VOC = 48 V, VTIP - VRING
Min -- -- -- -- -- 300 -- -- -- -- 93 82 --
Typ -- -- 320 -- 320 -- 10 10 4 1.5 -- -- 2 -- -- -- 2
Max 10 4 -- 4 -- -- 15 15 5 2 -- -- -- 1 50 600 4
Unit % V V k % % mA mA VPK VPK % % ms ms %
RDO VOHTO RROTO RTOTO
ILOOP < ILIM IRINGRinging Amplitude*
VRING
Open circuit, VBATH = 100 V 5 REN load, RLOOP = 0 , VBATH = 100 V
Sinusoidal Ringing Total Harmonic Distortion Ringing Frequency Accuracy Ringing Cadence Accuracy Calibration Time Loop Voltage Sense Accuracy Loop Current Sense Accuracy Power Alarm Threshold Accuracy
RTHD f = 16 Hz to 100 Hz Accuracy of ON/OFF times CAL to CAL bit Accuracy of boundaries for each output Code; VTIP - VRING = 48 V Accuracy of boundaries for each output code; ILOOP = 18 mA Power Threshold = 300 mW
-- -- -- --
--
7
10
%
--
--
25
%
*Note: Ringing amplitude is set for 93 V peak using the RINGAMP RAM address and measured at TIP-RING using no series protection resistance.
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SI3232
Table 6. Monitor ADC Characteristics
(VDD, VDD1-VDD4 = 3.13 to 3.47 V, TA = 0 to 70 C for K-Grade, -40 to 85 C for B-Grade)
Parameter Resolution Differential Nonlinearity Integral Nonlinearity Gain Error
Symbol
Test Condition
Min --
Typ 8 0.75 -- 0.6 0.1
Max -- -- +1.5 1.5 0.25
Unit Bits LSB LSB LSB LSB
DNL INL
-- -1.0 -- --
Table 7. Si3200 Characteristics
(VDD = 3.13 to 3.47 V, TA = 0 to 70 C for K-Grade, -40 to 85 C for B-Grade)
Parameter TIP/RING Pulldown Transistor Saturation Voltage
Symbol VCM
Test Condition VRING - VBAT (Forward), VTIP - VBAT (Reverse) ILIM = 22 mA, IABIAS = 4 mA1 ILIM = 45 mA, IABIAS = 16 mA1 GND - VTIP (Forward) GND - VRING (Reverse) ILIM = 22 mA1 ILIM = 45 mA1 (VBAT - VBATH)/IOUT (Note 2) RL = 0 VBAT - VBATL (Note 2)
Min
Typ
Max
Unit

3 4
--
V V
TIP/RING Pullup Transistor Saturation Voltage
VOV

3 4 15 0.8
-- 100
V V W A V
Battery Switch Saturation Impedance OPEN State TIP/RING Leakage Current Internal Blocking Diode Forward Voltage
Notes: 1. VAC = 2.5 VPK, RLOAD = 600 . 2. IOUT = 60 mA
RSAT ILKG VF
Preliminary Rev. 0.96
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SI3232
Table 8. DC Characteristics, VDDA = VDDD = VCC = 3.3 V
(VDD, VDD1-VDD4 = 3.13 V to 3.47 V, TA = 0 to 70 C for K-Grade, -40 to 85 C for B-Grade)
Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage
Symbol VIH VIL VOH VOL
Test Condition
Min 0.7 x VDD --
Typ -- -- -- -- -- 50 63 11 --
Max 3.47 0.3 x VDD -- 0.4 0.72 -- -- -- 10
Unit V V V V V k A
IO = 4 mA SDO, INT, SDITHRU IO = -4 mA BATSELa/b, GPOa/b: IO = -40 mA
VDD - 0.6
-- -- 35
SDITHRU Internal Pullup Resistance GPO Relay Driver Source Impedance GPO Relay Driver Sink Impedance Input Leakage Current ROUT RIN IL VDD1-VDD4 = 3.13 V, IO < 28 mA VDD1-VDD4 = 3.13 V, IO < 85 mA
-- -- --
Note: All timing (except Rise and Fall time) is referenced to the 50% level of the waveform. Input test levels are VIH = VDD - 0.4 V, VIL = 0.4 V. Rise and Fall times are referenced to the 20% and 80% levels of the waveform.
Table 9. Switching Characteristics--General Inputs
(VDD, VDD1-VDD4 = 3.13 to 3.47 V, TA = 0 to 70 C for K-Grade, -40 to 85 C for B-Grade, CL = 20 pF)
Parameter Rise Time, RESET RESET Pulse Width* RESET Pulse Width*, SDI Daisy Chain Mode
Symbol tr trl trl
Min -- 500 6
Typ -- -- --
Max 5 -- --
Unit ns ns s
*Note: The minimum RESET pulse width assumes the SDITHRU pin is tied to ground via a pulldown resistor no greater than 10 k per device.
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SI3232
Table 10. Switching Characteristics--SPI
(VDD, VDD1-VDD4 = 3.13 to 3.47 V, TA = 0 to 70 C for K-Grade, -40 to 85 C for B-Grade, CL = 20 pF)
Parameter Cycle Time SCLK Rise Time, SCLK Fall Time, SCLK Delay Time, SCLK Fall to SDO Transition Delay Time, CS Rise to SDO Tristate Setup Time, CS to SCLK Rise Hold Time, SCLK Rise to CS Rise Setup Time, SDI to SCLK Rise Hold Time, SCLK Rise to SDI Rise SDI to SDITHRU Propagation Delay
Symbol tc tr tf td2 td3 tsu1 th1 tsu2 th2
Test Conditions
Min 0.062 -- -- -- -- 15 20 25 20 --
Typ -- -- -- -- -- -- -- -- -- 6
Max -- 25 25 20 20 -- -- -- -- --
Unit s ns ns ns ns ns ns ns ns ns
Note: All timing is referenced to the 50% level of the waveform. Input test levels are VIH - VDD -0.4 V, VIL = 0.4 V
tr tr tc
SCLK
CS
tsu1
th1
tsu2
th2
SDI
td2 td3
SDO
Figure 1. SPI Timing Diagram
Preliminary Rev. 0.96
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SI3232
Table 11. Switching Characteristics--PCLK and FSYNC Timing
(VDD, VDD1-VDD4 = 3.13 to 3.47 V, TA = 0 to 70 C for K-Grade, -40 to 85 C for B-Grade, CL = 20 pF)
Parameter PCLK Period Valid PCLK Inputs
Symbol tp
Test Conditions
Min 1 122 -- -- -- -- -- -- -- -- --
Typ 1 -- 256 512 768 1.024 1.536 1.544 2.048 4.096 8.192 125 50 -- -- -- -- -- --
Max 1 3706 -- -- -- -- -- -- -- -- -- -- 60 120 25 25 -- -- 125 s-tp
Units ns kHz kHz kHz MHz MHz MHz MHz MHz MHz s % ns ns ns ns ns ns
FSYNC Period2 PCLK Duty Cycle Tolerance PCLK Period Jitter Tolerance Rise Time, PCLK Fall Time, PCLK Setup Time, FSYNC to PCLK Fall Hold Time, FSYNC to PCLK Fall FSYNC Pulse Width
tfs tdty tjitter tr tf tsu1 th1 twfs
-- 40 -- -- -- 25 20 tp/2
Notes: 1. All timing is referenced to the 50% level of the waveform. Input test levels are VIH - VI/O -0.4 V, VIL = 0.4 V. 2. FSYNC source is assumed to be 8 kHz under all operating conditions.
tp PCLK th1 tfs
tr
tf
FSYNC
tsu1
Figure 2. PCLK, FSYNC Timing Diagram
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SI3232
Pulse Metering Detection To DSP ATX Mute
+
To off-chip A/D
Codec Loopback
TIP/ RING
ZA
Ibuf Gm
+
Mute D/A Pulse Metering DAC Pulse Metering Generation
From off-chip ARX D/A
Figure 3. SI3232 Simplified Audio Path Block Diagram
9 8 7 6
Fundamental Output Power 5 (dBm0) Acceptable Region
4 3
2.6
2 1 0 1 2 3 4 5 6 7 8 9
Fundamental Input Power (dBm0)
Figure 4. Overload Compression Performance
Preliminary Rev. 0.96
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SI3232
VBAT
C41 3.3 nF
VRXP
C42 3.3 nF
VRXPa VRXNa
C43 3.3 nF
SRINGDCa SRINGACa STIPDCa TIP
VRXN
C45
150 pF
VTXP
R40 20 k
VTXPa
SRINGDACa ITIPPa
VTXN
C47 150 pF
R41 20 k
VTXNa
IRINGNa IRINGPa
Si3200
BCM3341
C46
150 pF
CMlevel
VCM
INT SCLK CS SDI SDO
RING ITIPNa
SPI Port
SI3232
Figure 5. Typical Connection Diagram between SI3232 and Broadcom(R) BCM3341 (One SLIC channel shown: Channel "a")
16
Preliminary Rev. 0.96
VDD VDD JCP4
J1 U2 VRXP +5V VDD VBLO R6 VRXPa R2 VRXNa C2 R4 VTXNa R3 R1 0.1u U1 402k 4.7k TIPa_EXT 4.7k VTXPa C1 C24 0.1u 100V X7R 0.1u 100V X7R DETn /RESET 402k VBHI 40.2k VTXP
TP1 Tip A
R20 390
CMLevel
VTXN VRXN
1
Protection
TIPa_ext
TIPa
TIPa
RINGa_ext RINGa
RINGa
6 5 4 3 2 1
C30 0.1u 100V Si3200 VBLO VBHI R21 15 C32 0.1u 100V
RJ-11 SMD
Ring A TP2
1
1 2 3 4 5 6 7 8 TIP NC RING VBAT VBATH VBATL GND VDD GND epad ITIPP ITIPN THERM IRINGP IRINGN NC NC BATSEL
16 15 14 13 12 11 10 9
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
con50_champ_m AMP 5-175473-6 J2
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
RINGa_EXT
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
R24 39k
STIPDCa STIPACa SRINGACa SRINGDCa ITIPNa IRINGNa ITIPPa VDD1 GND1 IRINGPa THERMa VRXPa VRXNa VTXPa VTXNa BATSELa
C3 10n 100V R5 R8 R7 C5 1u 6V R10 C15 R17 R18 R15 182 806k 182 C16 40.2k 1u 6V C6 182 182 806k
C4 10n 100V
DETn
TP5 TP6 TP7 TP8 GNDGNDGNDGND
1 2
/CS SDITHRU SDI SDO SCLK /INT PCLK J3
GPOa
1
1
1
1
2. Typical Application Schematic
SI3232
STIPDCb STIPACb SRINGACb SRINGDCb ITIPNb IRINGNb ITIPPb VDD2 GND2 IRINGPb THERMb VCM VRXPb VRXNb VTXPb VTXNb
C13 10n 100V
C14 10n 100V
1u 6V
1u 6V
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SVBATa RPOa RPIa RNIa RNOa CAPPa CAPMa QGND IREF CAPMb CAPPb RNOb RNIb RPIb RPOb SVBATb GPOa /CS SDITHRU SDI SDO SCLK VDD4 GND4 /INT PCLK GND3 VDD3 GPOb BATSELB FSYNC /RST
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
1 2
FSYNC /RESET
GPOb
VTXP VTXN VTXNb VTXPb
J11
1
RJ-11 SMD R23 15 C23 0.1u VBHI VBLO Si3200 C31 0.1u 100V C33 0.1u 100V
Ring B TP4
1 2 3 4 5 6 7 8 TIP NC RING VBAT VBATH VBATL GND VDD
R16
ITIPP ITIPN THERM IRINGP IRINGN NC NC BATSEL GND epad
16 15 14 13 12 11 10 9
40.2k
VRXP VRXN
6 5 4 3 2 1
1
Preliminary Rev. 0.96
R11 C11 R13 R14 R12 402k 4.7k VRXNb VRXPb CMLevel 4.7k C12 R22 VDD U3 390 402k
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Channel
JP3 VTXPa VTXP VTXPb VRXPa VRXP VRXPb
TP3 Tip B
0.1u 100V X7R 0.1u 100V X7R
1 3 5
1 3 5
2 4 6
2 4 6
VTXNa VTXN VTXNb VRXNa VRXN VRXNb
a b
Protection
a b
1 3 5 1 3 5
JP4
TIPb_ext
TIPb
TIPb
2 4 6
2 4 6
RINGb_ext RINGb
RINGb
SI3232
17
SI3232
3. Bill of Materials
Component C1, C2, C11, C12 C3, C4, C13, C14 C5, C6, C15, C16 C20-C25 C30-C33 C41-43* C45-47* R1, R2, R11, R12 R3, R4, R13, R14 R5, R15 R6, R16 R7, R8, R17, R18 R10 R40, R41* Value 100 nF, 100 V, X7R, 20% 10 nF, 100 V, X7R, 20% 1 F, 10 V, X7R, 20% 0.1 F, 10 V, Y5V 0.1 F, 100 V, Y5V 3.3 nF, 10 V, X7R, 20% 150 nF, 10 V, X7R, 20% 402 k, 1/10 W, 1% 4.7 k, 1/10 W, 5% 806 k, 1/10 W, 1% 40.2 k, 1/10 W, 5% 182 , 1/10 W, 1% 40.2 k, 1/10 W, 1% 20 k, 1/10 W, 1% Function Filter capacitors for TIP, RING ac-sensing inputs. TIP/RING compensation capacitors. Low-pass filter capacitor to stabilize differential and common mode SLIC feedback loops. Decoupling for analog and digital chip supply pins. Decoupling for battery voltage supply pins. Reconstruction filter for DAC of BCM3341. Anti-aliasing filter for ADC of BCM3341. Sense resistors for TIP, RING dc sensing nodes. Current limiting resistors for TIP, RING ac-sensing inputs. Sense resistor for battery voltage sensing node. Sets bias current for battery switching logic circuit. Reference resistors for internal transconductance amplifier. Generates a high accuracy reference current. Anti-aliasing filter for ADC of BCM3341.
*Note: These components are only required when used with BCM3341 and other interface-compatible Broadcom products.
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Preliminary Rev. 0.96
SI3232
4. Functional Description
The SI3232 dual SLIC is a low-voltage CMOS device that provides a fully-programmable SLIC with line monitoring and test functions to create a dual-channel analog telephone interface. Intended for multiple channel applications, the SI3232 provides high integration and low-power operation for applications, such as integrated access devices (IADs), voice-over DSL systems, cable telephony systems, and voice-over IP systems. These devices meet all relevant Bellcore LSSGR, ITU, and ETSI standards. The SI3232 performs the battery, overvoltage, ringing, supervision, hybrid, and test functions on-chip in a lowpower, small-footprint solution. All high-voltage functions are implemented using the Si3200 linefeed interface IC allowing a highly-integrated solution that offers the lowest total system cost. The internal linefeed circuitry provides programmable on-hook voltage and off-hook loop current, reverse battery operation, loop or ground start operation, and on-hook transmission. Loop current and voltage are continuously monitored using an integrated 8-bit monitor A/D converter. The SI3232 provides on-chip, balanced, 5 REN ringing with or without a programmable dc offset eliminating the need for an external bulk ring generator and per-channel ringing relay typically used in unbalanced ringing applications. Both sinusoidal and trapezoidal ringing waveshapes are available. Ringing parameters, such as frequency, waveshape, cadence, and offset, can be programmed into registers to reduce external controller requirements. All ringing options are software-programmable over a wide range of parameters to address a wide variety of application requirements. The SI3232 also provides a variety of line monitoring and subscriber loop testing. It has the ability to continuously monitor and store all line voltage and current parameters for fault detection, and all values are available in registers for later use. In addition, the SI3232 provides line card and subscriber loop diagnostic functions to eliminate the need for systemlevel test equipment. These test and diagnostic functions are intended to comply with relevant LSSGR and ITU requirements for line-fault detection and reporting, and all measured values are stored in registers for later use or further calculations. The SI3232 is software-programmable allowing a single hardware design to meet international requirements. Programmability is supported using a standard 4-wire serial peripheral interface (SPI). The SI3232 is available in a 64-lead thin quad flat package (TQFP), and the Si3200 is available in a thermally-enhanced 16-lead SOIC.
4.1. Linefeed Architecture
The SI3232 is a low-voltage CMOS device that uses a low-cost integrated linefeed interface IC to control the high voltages required for subscriber line interfaces. Figure 6 is a simplified single-ended model of the linefeed control loop circuit for both the TIP and RING leads. The SI3232 uses both voltage and current sensing to control TIP and RING. DC line voltages on TIP and RING are measured through sense resistors RDC. AC line voltages on TIP and RING are measured through sense resistors RAC. The SI3232 uses the Si3200 linefeed interface to drive TIP and RING. The SI3232 measures voltage at various nodes to monitor the linefeed current. RDC and RBAT provide access to these measuring points. The sense circuitry is calibrated on-chip to guarantee measurement accuracy. See "4.4. Linefeed Calibration" on page 25 for details on linefeed calibration.
4.2. Power Supply Transients on the Si3200
The Si3200 features an ESD clamp protection circuit connected between the VDD and VBATH rails. This clamp protects the Si3200 against ESD damage when the device is being handled out-of-circuit during manufacture. Precautions must be taken in the VDD and VBATH system power supply design. At power-up, the VDD and VBATH rails must ramp-up from 0 V to their respective target values in a linear fashion and must not exhibit fast transients or oscillations which could cause the ESD clamp to be activated for an extended period of time resulting in damage to the Si3200. The resistors shown as R20 through R23 together with capacitors C23, C24, C30 and C31 in the Application Schematic (Figure on page 17) provide some measure of protection against in-circuit ESD clamp activation by forming a filter time constant and by providing current limitting action in case of momentary clamp activation during power-up. These resistors and capacitors must be included in the application circuit, while ensuring that the VDD and VBATH system power supplies are designed to exhibit start-up behavior that is free of undesirable transients or oscillations. Once the VDD and VBATH are in their steady state final values, the ESD clamp has circuitry that prevents it from being activated by transients slower than 10 V/us. In the steady powered-up state, the VDD and VBATH rails must therefore not exhibit transients resulting in a voltage slew rate greater than 10 V/s.
Preliminary Rev. 0.96
19
SI3232
SI3232
Monitor A/D A/D A/D
Pulse Metering
DSP
D/A D/A SLIC DAC
Audio Control
STIPDC/SRINGDC ITIPN/IRINGN ITIPP/IRINGP
SLIC Control
VBAT Sense
STIPAC/SRINGAC
BATSEL
Audio Control Loop
SLIC Control Loop
SVBAT RBAT
CAC
RDC
Si3200
TIP or RING
Current Mirror VBATL VBAT
Battery Select Control
VBATH
Figure 6. Simplified Linefeed Architecture for TIP and RING Leads (Diagram illustrates either TIP or RING lead of a single channel)
4.3. DC Feed Characteristics
The SI3232 offers programmable constant voltage and constant current operating regions as illustrated in Figure 7 and Figure 8. The constant voltage region is defined by the open-circuit voltage, VOC, and is programmable from 0 to 63.3 V in 1 V steps. The constant current region is defined by the loop current limit, ILIM, and is programmable from 18 to 45 mA in 0.87 mA steps. The SI3232 exhibits a characteristic dc impedance of 320 during Active mode. The TIP-RING voltage, VOC, is offset from ground by a programmable voltage, VCM, to provide sufficient voltage headroom to the most positive terminal (typically the TIP lead in normal polarity or the RING lead in reverse polarity) for carrying audio signals. A similar programmable voltage, VOV, is provided as an offset between the most negative terminal and the battery supply rail for carrying audio signals. (See Figure 7.) The user-supplied battery voltage must have sufficient amplitude under all operating states to ensure sufficient headroom. The Si3200 may be powered by a lower secondary battery supply, VBATL, to reduce total power dissipation when driving short loop lengths.
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Preliminary Rev. 0.96
SI3232
Loop Closure Threshold R Constant V Region LOOP VCM VTIP VOC
The minimum battery supply required can be calculated according to the following equation.
V BAT V OC + V CM + V OV
Constant I Region
VCM and VOV are provided in Table 8. The default VCM value of 3 V provides sufficient overhead for a 3.1 dBm signal into a 600 loop impedance.
VOV VBATL V
Secondary VBAT Selected
VOV
VRING VBATH
A VOV value of 4 V provides sufficient headroom to source a maximum ILOOP of 45 mA along with a 3.1 dBm audio signal and an ABIAS setting of 16 mA. For a typical operating condition, VBAT = -56 V and ILIM = 22 mA: VOC,MAX = 56 V - (3 V + 4 V) = 49 V These conditions apply when the dc-sensing inputs, STIPDCa/b and SRINGDCa/b, are placed on the SLIC side of any protection resistance placed in series with the TIP and RING leads. If line-side sensing is desired, both VOV and VCM must be increased by a voltage equal to RPROT x ILIM where RPROT is the value of each protection resistor. Other safety precautions may apply. See "4.7.3. Linefeed Overhead Voltage Considerations During Ringing" on page 40 for details on calculating the overhead voltage during the ringing state. The SI3232 uses both voltage and current information to control TIP and RING. Sense resistor RDC (see Figure 6) measures dc line voltages on TIP and RING; capacitor CAC couples the ac line voltages on the TIP and RING leads to be measured. The SI3232 uses the Si3200 linefeed interface IC to drive TIP and RING and to isolate the high-voltage line from the low-voltage SI3232. The SI3232 measures voltage at various nodes to monitor the linefeed current. RDC and RBAT provide these measuring points. The sense circuitry is calibrated on-chip to ensure measurement accuracy. See "4.4. Linefeed Calibration" on page 25 for details.
Figure 7. DC Linefeed Overhead Voltages (Forward State)
4.3.1. Calculating Overhead Voltages The two programmable overhead voltages, VOV and VCM, represent one portion of the total voltage between VBAT and ground as illustrated in Figure 7. In normal operating conditions, these overhead voltages are sufficiently low to maintain the desired TIP-RING voltage, VOC. There are, however, certain conditions under which the user must exercise care in providing a battery supply with enough amplitude to supply the required TIP-RING voltage as well as enough margin to accommodate these overhead voltages. The VCM voltage is programmed for a given operating condition. Therefore, the open-circuit voltage, VOC, varies according to the required overhead voltage, VOV, and the supplied battery voltage, VBAT. The user should pay special attention to the maximum VOV and VCM that might be required for each operating state. In the off-hook active state, sufficient VOC must be maintained to correctly power the phone from the battery supply that has been provided. Since the battery supply depends on the state of the input supply (i.e., charging, discharging, or battery backup mode), the user must decide how much loop current is required and determine the maximum loop impedance that can be driven based on the battery supply provided.
Preliminary Rev. 0.96
21
SI3232
4.3.2. Linefeed Operation States The linefeed interface includes eight different operating states as described in Table 12. The Linefeed register settings (LF[2:0], Linefeed Register) are also listed. The Open state is the default condition in the absence of any pre-loaded register settings. The device may also automatically enter the Open state if any excess power consumption is detected in the Si3200. See "4.4.3. Power Monitoring and Power Fault Detection" on page 26 for more details. The register and RAM locations used for programming the linefeed parameters are provided in Table 13. Also see "4.4.2. Loop Voltage and Current Monitoring" and "4.4.3. Power Monitoring and Power Fault Detection" on page 26 for more detailed descriptions and register/ RAM locations for these specific functions.
Table 12. Linefeed States
Open (LF[2:0] = 000). The Si3200 output is high-impedance. This mode can be used in the presence of line fault conditions and to generate Open Switch Intervals (OSIs). The device can also automatically enter the Open state if any excess power consumption is detected in the Si3200. Forward Active (LF[2:0] = 001). Linefeed is active, but audio paths are powered down until an off-hook condition is detected. The SI3232 will automatically enter a low-power state to reduce power consumption during on-hook standby periods. Forward On-Hook Transmission (LF[2:0] = 010). Provides data transmission during an on-hook loop condition (e.g., transmitting FSK caller ID information between ringing bursts). Tip Open (LF[2:0] = 011). Sets the portion of the linefeed interface connected to the TIP side of the subscriber loop to high impedance and provides an active linefeed on the RING side of the loop for ground start operation. Ringing (LF[2:0] = 100). Drives programmable ringing waveforms onto the subscriber loop. Reverse Active (LF[2:0] = 101). Linefeed circuitry is active, but audio paths are powered down until an off-hook condition is detected. The SI3232 will automatically enter a low-power state to reduce power consumption during on-hook standby periods. Reverse On-Hook Transmission (LF[2:0] = 110). Provide data transmission during an on-hook loop condition. Ring Open (LF[2:0] = 111). Sets the portion of the linefeed interface connected to the RING side of the subscriber loop to high impedance and provides an active linefeed on the TIP side of the loop for ground start operation.
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Preliminary Rev. 0.96
SI3232
Table 13. Register and RAM Locations used for Linefeed Control
Parameter Register / RAM Mnemonic LINEFEED LINEFEED RLYCON ILIM VOC VCM VOCDELTA VOCLTH VOCHTH VOV VOVRING VOCTRACK Register/RAM Bits Programmable Range See Table 12 Monitor only VBATH/VBATL 18-45 mA 0 to 63.3 V 0 to 63.3 V 0 to 63.3 V 0 to 63.3 V 0 to 63.3 V 0 to 63.3 V 0 to 63.3 V 0 to 63.3 V LSB Size Effective Resolution N/A N/A N/A 0.875 mA 1.005 V 1.005 V 1.005 V 1.005 V 1.005 V 1.005 V 1.005 V 1.005 V
Linefeed Linefeed Shadow Battery Feed Control Loop Current Limit On-Hook Line Voltage Common Mode Voltage VOC Delta for Off-Hook VOC Delta Threshold, Low VOC Delta Threshold, High Overhead Voltage Ringing Overhead Voltage VOC During Battery Tracking
LF[2:0] LFS[2:0] BATSEL ILIM[4:0] VOC[14:0] VCM[14:0] VOCDELTA[14:0] VOCTHD[15:0] VOCTHD[15:0] VOV[14:0] VOVRING[14:0] VOCTRACK[15:0]
N/A N/A N/A 0.875 mV 4.907 mV 4.907 mV 4.907 mV 4.907 mV 4.907 mV 4.907 mV 4.907 mV 4.907 mV
The dc linefeed circuitry generates the necessary TIP/RING I/V characteristics along with loop closure and ring trip detection. For loop start applications, VTIP-VRING is programmable. The loop current limit, ILIM, is softwareprogrammable with a range from 18-45 mA.
60 50 40 RO = 600
Loop Closure Threshold R O = 320
VOC
VTIP- RING (V)
30 20 10
I LIM
I LIM = 24 mA
0
10
20
30
40
50
ILOOP (mA)
Figure 8. VTIP-RING vs. ILOOP Characteristic for Loop Start Operation
Preliminary Rev. 0.96
23
SI3232
IRING (mA)
0
10
20
30
40
50
debouncing is provided. A high-gain common-mode loop generates a low impedance from TIP or RING to ground, effectively reducing the effects of longitudinal interference. For ground-start operation, the active lead presents a 640 output impedance during the on-hook state and a 320 output impedance in the off-hook state. The "open" lead presents a high-impedance feed (>150 k). Figure 9 illustrates a typical ground-start application using VOC = 48 V and ILIM = 24 mA in the TIP OPEN state. The ring ground-detection threshold and debouncing interval are both programmable.
VTIP- RING (V)
50
VOCDELTA
VRING (V)
ILIM = 24 mA
-20
Loop Closure Threshold
-40
RO = 600 RO = 320
-60
Figure 9. VRING vs. IRING Characteristic for Ground Start Operation
Figure 8 illustrates the linefeed characteristics for a typical application using an ILOOP setting of 24 mA and a TIP-RING open circuit voltage (VOC) of 48 V. The VOC and VOCTRACK RAM locations are used to program the TIP-RING voltage, and these two values are equal provided that VBAT > VOC + VOV + VCM. When the battery voltage drops below that point, VOCTRACK decreases at the same rate as VBAT in order to provide sufficient headroom to accommodate both VOV and VCM levels below VBAT. The equation for calculating the RAM address value for VOC, VCM, VOCDELTA, VOV, VOVRING, RINGOF, VOCLTH, and VOCHTH is shown below. The CEILING function rounds up the result to the next integer.
RAM VALUE = desired voltage 512 2 x CEILING ROUND --------------------------------------- x --------- 1.005V 5
RO = 320
VOC
40 30 RO = 600 20 10 1930 load line
VOCTRACK
0
10
20
I LIM (mA)
Figure 10. VTIP-RING vs. ILOOP Characteristics using Modified Linefeed Scheme
The modified linefeed scheme also allows the user to modify the apparent VOC voltage as a means of boosting the linefeed voltage when the battery voltage drops below a certain level. Figure 10 illustrates a typical SI3232 application sourcing a loop from a 48 V battery. For VOV and VCM values of 3 V, the VOCTRACK RAM location will be set to 42 V when given a programmed value of 42 V for the VOC RAM location. When a loop closure event occurs, the TIPRING voltage decreases linearly until it reaches a preset voltage threshold that is lower than VOCTRACK by an amount programmed into the VOCLTH RAM location. Exceeding this threshold causes the Dual ProSLIC to increase its "target" VOC level by an amount programmed into the VOCDELTA RAM location to provide additional overhead for driving the higherimpedance loop. In the on-hook condition, the TIPRING voltage increases linearly until it rises above a second preprogrammed voltage threshold, which is higher than VOCTRACK by an amount programmed into the VOCHTH RAM location. This scheme offers the ability to drive very long loop lengths while using the lowest possible battery voltage. Consult the factory for optimal register and RAM location settings for specific applications.
For example, to program a VOC value of 51 V:
512 51 V VOC = 2 x CEILING ROUND ------------------- x --------- = 28CEh 1.005 V 5
During the on-hook state, the SI3232 is in the constantvoltage operating area and typically presents a 640 output impedance (Figure 8). The SI3232 includes a special modified linefeed scheme that adjusts the ProSLIC's output impedance based on the linefeed voltage level in order to ensure the ability to source extended loop lengths. When the terminal equipment transitions to the off-hook state, the linefeed voltage typically collapses and transitions through the preset threshold voltage causing the SI3232 to reduce its output impedance to 320 . The TIP-RING voltage will then continue decreasing until the preset loop current limit (ILIM) setting is reached. Loop closure and ring trip detection thresholds are programmable, and internal
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Preliminary Rev. 0.96
SI3232
Table 14. Register and RAM Locations used for Loop Monitoring
Parameter Loop Voltage Sense (VTIP - VRING) TIP Voltage Sense RING Voltage Sense Loop Current Sense Longitudinal Current Sense Battery Voltage Sense Register/RAM Mnemonic VLOOP VTIP VRING ILOOP ILONG VBAT Register/ RAM Bits VLOOP[15:0] VTIP[15:0] VRING[15:0] ILOOP[15:0] ILONG[15:0] VBAT[15:0] Measurement Range 0 to 64.07 V 64.07 to 160.173 V 0 to 64.07 V 64.07 V to 160.173 V 0 to 64.07 V 64.07 V to 160.173 mA 0 to 101.09 mA 0 to 101.09 mA 0 to 64.07 V 64.07 to 160.173 V LSB Size 4.907 mV 4.907 mV 4.907 mV 3.907 A 3.907 A 4.907 mV Effective Resolution 251 mV 628 mV 251 mV 628 mV 251 mV 628 mV 500 A* 500 A* 251 mV 628 mV
*Note: ILOOP and ILONG are calculated values based on measured IQ1-IQ4 currents. The resulting effective resolution is approximately 500 A.
4.4. Linefeed Calibration
An internal calibration algorithm corrects for internal and external component errors. The calibration is initiated by setting the CAL register bit. Upon completion of the calibration cycle, this bit is automatically reset. It is recommended that a calibration be executed following system powerup. Upon release of the chip reset, the device is in the Open state, and calibration can be initiated. Only one calibration should be necessary as long as the system remains powered up. The Dual ProSLIC calibration sequence consists of SLIC mode calibration, monitor ADC calibration, and audio path calibration. The calibration bits that are set in registers CALR1 and CALR2 are executed in order of MSB to LSB for each sequential register. CALR1, bit 7 starts the calibration sequence. CALR2 calibration bits should be set before the CALR1 is written. The reserved bit (bit 6) of CALR1 must always be cleared to 0. The interrupt bit, bit 7 of IRQ3, will report an error in the calibration process. The error could include the line becoming off-hook during the common mode balance calibration. During all calibrations, the calibration engine controls VTIP and VRING to provide the correct external voltage conditions for the calibration algorithm. The TIP and RING leads must not be connected to ground during any calibration. The leakage calibrations (CALR1, bits 4-5) can be done at regular intervals to provide optimal performance over temperature variations. The TIP/RING leakage calibrations can be performed every hour. Invoke these leakage calibrations, only during on-hook, by setting
CALR1 to 0xB0. The leakage calibration takes 5 ms and interferes with dc feed and voice transmission during its process. 4.4.1. Common Mode Calibration To optimize common mode (longitudinal) balance performance, it is recommended that the user perform the following steps when running the common-mode calibration routine: 1. Write the Register values as shown in Table 15. These coefficient values select a 600 impedance synthesis 2. Set Common Mode Balance Interrupt (IRQEN3 = 0x80) 3. Set CALR2 = 0x01. This enables only the AC longitudinal balance calibration routine (CALCMBAL) 4. Set CALR2 = 0x80. This begins the calibration process. 5. Wait for the CALR1 register to clear to 0x0, indicating the longitudinal balance calibration is complete (up to 100ms). 6. Ensure that a common mode balance error interrupt did not occur. Retry calibration if true. 7. Rewrite desired register values that were changed during this calibration. During all calibrations, the calibration engine controls VTIP and VRING to provide the correct external voltage conditions for the calibration algorithm. The TIP and RING leads must not be connected to ground during any calibration. Note that the channel being calibrated must be on-hook.
Preliminary Rev. 0.96
25
SI3232
Table 15. Register Values for CM Calibration (600 Impedance Synthesis)
Register Name ZRS ZZ Register Location (decimal) 33 34 Register Value (hexadecimal) 0x5 0x1 protect the high-voltage circuitry against excessive power dissipation and thermal-overload conditions. The SI3232 also has the ability to prevent thermal overloads by regulating the total power inside the Si3200 or in each of the external bipolar transistors (if using a discrete linefeed circuit). The DSP engine performs all power calculations and provides the ability to automatically transition the device into the OPEN state and generate a power alarm interrupt when excessive power is detected. Table 16 describes the register and RAM locations used for power monitoring. 4.4.4. Transistor Power Equations (Using Discrete Transistors) When using the SI3232 along with discrete bipolar transistors, it is possible to control the total power of the solution by regulating the power in each discrete transistor individually. Figure 11 illustrates the basic transistor-based linefeed circuit for one channel. The power dissipation of each external transistor is estimated based on the A/D sample values. The approximate power equations for each external BJT are as follows: PQ1 VCE1 x IQ1 (|VTIP| + 0.75 V) x (IQ1) PQ2 VCE2 x IQ2 (|VRING| + 0.75 V) x (IQ2) PQ3 VCE3 x IQ3 (|VBAT| - R7 x IQ5) x (IQ3) PQ4 VCE4 x IQ4 (|VBAT| - R6 x IQ6) x (IQ4) PQ5 VCE5 x IQ5 (|VBAT| - |VRING| - R7 x IQ5) x (IQ5) PQ6 VCE6 x IQ6 (|VBAT| - |VTIP| - R6 x IQ6) x (IQ6)
IRINGP IRINGN
4.4.2. Loop Voltage and Current Monitoring The SI3232 continuously monitors the TIP and RING voltages and currents. These values are available to the user in registers. An internal 8-bit A/D converter samples the measured voltages and currents from the analog sense circuitry and translates them into the digital domain. The A/D updates the samples at an 800 Hz rate. Two derived values, the loop voltage (VTIP - VRING) and the loop current are also reported. For ground start operation, the values reported are VRING and the current flowing in the RING lead. Table 14 lists the register set associated with the loop monitoring functions. The SI3232 also includes the ability to perform loop diagnostics functions as outlined in "4.18.2. Line Test and Diagnostics" on page 57. 4.4.3. Power Monitoring and Power Fault Detection The SI3232 line monitoring functions can be used to
ITIPN ITIPP
Q4
Q1
Q2
Q3
RBQ6
TIP
RING
RBQ5
Q8
Q7
Q10
Q6
Q5
Q9
R6*gain 1.74k
R6 82.5
R7 82.5 1.74k
R7*gain VBAT
Figure 11. Discrete Linefeed Circuit for Power Monitoring
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The maximum power threshold for each device is software-programmable and should be set based on the characteristics of the transistor package, PCB design, and available airflow. If the peak power exceeds the programmed threshold for any device, the power alarm bit is set for that device. Each external bipolar has its own register bit (PQ1S-PQ6S bits of the IRQVEC3 register) which goes high on a rising edge of the comparator output and remains high until the user clears it. Each transistor power alarm bit is also maskable by setting the PQ1E-PQ6E bits in the IRQEN3 register. 4.4.5. Si3200 Power Calculation When using the Si3200, it is also possible to detect the thermal conditions of the linefeed circuit by calculating the total power dissipated within the Si3200. This case is similar to the Transistor Power Equations case, with the exception that the total power from all transistor devices is dissipated within the same package enclosure and the total power result is placed in the PSUM RAM location. The power calculation is derived using the following set of equations: PQ1 (|VTIP| + 0.75 V) x IQ1 PQ2 (|VRING| + 0.75 V) x IQ2 PQ3 (|VBAT|+ 0.75 V) x IQ3 PQ4 (|VBAT| + 0.75 V) x IQ4 PQ5 (|VBAT| - |VRING|) x IQ5 PQ6 (|VBAT| - |VTIP|) x IQ6 PSUM = total dissipated power = PQ1 + PQ2 + PQ3 + PQ4 + PQ5 + PQ6
Note: The Si3200 THERM pin must be connected to the THERM a/b pin of the SI3232 in order for the Si3200 power calculation to work correctly.
3 4096 PLPFxx (decimal value) = ------------------------------------ x 2 800 x thermal
where 4096 is the maximum value of the 12-bit plus sign RAM locations, PLPF12, PLPF34, and PLPF56, and 800 is the power calculation clock rate in Hz. The equation is an excellent approximation of the exact equation for thermal = 1.25 ms ... 5.12 s. With the above equations in mind, example values of the RAM locations, PTH12, PTH34, PTH56, PLPF12, PLPF34, and PLPF56 follow: PTH12 = power threshold for Q1, Q2 = 0.3 W (0x25A) PTH34 = power (0x1BSE) threshold for Q3, Q4 = 0.22 W
PTH56 = power threshold for Q5, Q6 = 1 W (0x7D8) PLPF12 = Q1/Q2 Thermal LPF pole = 0x0012 (for SOT89 package) PLPF34 = Q3/Q4 Thermal LPF pole = 0x008C (for SOT-23 package) PLPF56 = Q5/Q6 thermal LPF pole = 0x000E (for SOT223 package) When Si3200 is used, the thermal filtering needs to be performed on the total power reflected in the PSUM RAM location. When the filter output exceeds the total power threshold, an interrupt is issued. The PTH12 RAM location is used to preset the total power threshold for the Si3200, and the PLPF12 RAM location is used to preset the thermal low-pass filter pole. When the THERM pin is connected from the SI3232 to the Si3200 (indicating the presence of an Si3200), the resolution of the PTH12 and PSUM RAM locations is modified from 498 W/LSB to 1059.6 W/LSB. Additionally, the THERMAL value must be modified to accommodate the Si3200. THERMAL for the Si3200 is typically 0.7 s assuming the exposed pad is connected to the recommended ground plane as stated in Table 1. THERMAL decreases if the PCB layout does not provide sufficient thermal conduction. See "AN58: Si3220/ Si3225 Programmer's Guide" for details. Example calculations for PTH12 and PLPF12 in Si3200 mode are shown below: PTH12 = Si3200 power threshold = 1 W (0x3B0) PLPF12 = Si3200 thermal LPF pole = 2 (0x0010) 4.4.7. Automatic State Change Based on Power Alarm If any of the following situations occurs, the device automatically transitions to the OPEN state: Any of the transistor power alarm thresholds is exceeded (in the case of the discrete transistor circuit).
4.4.6. Power Filter and Alarms The power calculated during each A/D sample period must be filtered before being compared to a userprogrammable maximum-power threshold. A simple digital low-pass filter is used to approximate the transient thermal behavior of the package, with the output of the filter representing the effective peak power within the package or, equivalently, the peak junction temperature. For Q1, Q2, Q3, Q4 in SOT23 and Q5, and Q6 in SOT223 packages, the settings for thermal low-pass filter poles and power threshold settings are (for an ambient temperature of 70 C) calculated as follows: Suppose that the thermal time constant of the package is thermal. The decimal values of RAM locations PLPF12, PLPF34, and PLPF56 are given by rounding to the next integer the value given by the following equation:
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The total power threshold is exceeded (when using the power calculator method along with the Si3200). To provide optimal reliability, the device automatically transitions into the open state until the user changes the state manually, independent of whether or not the power alarm interrupt has been masked. The PQ1E to PQ6E bits of the IRQEN3 register are used to enable the interrupts for each transistor power alarm, and the PQ1S to PQ6S bits of the IRQVEC3 register are set when a power alarm is triggered in the respective transistor. When using the Si3200, the PQ1E bit is used to enable the power alarm interrupt, and the PQ1S bit is set when a Si3200 power alarm is triggered. 4.4.8. Power Dissipation Considerations The SI3232 relies on the Si3200 to power the line from the battery supply. The PCB layout and enclosure conditions should be designed to allow sufficient thermal dissipation out of the Si3200, and a programmable power alarm threshold ensures product safety under all operating conditions. See "4.4.3. Power Monitoring and Power Fault Detection" for more details on power alarm considerations. The Si3200's thermallyenhanced SOIC-16 package offers an exposed pad that improves thermal dissipation out of the package when soldered to a topside PCB pad connected to inner power planes. Using appropriate layout practices, the Si3200 can provide thermal performance of 55 C/W. The exposed path should be connected to a lowimpedance ground plane via a topside PCB pad directly under the part. See package outlines for PCB pad dimensions. In addition, an opposite-side PCB pad with multiple vias connecting it to the topside pad directly under the exposed pad further improves the overall thermal performance of the system. Refer to "AN55: Dual ProSLICTM User Guide" or the SI3232 evaluation board data sheet for layout guidelines for optimal thermal dissipation.
Table 16. Register and RAM Locations used for Power Monitoring and Power Fault Detection
Parameter Si3200 Power Output Monitor Si3200 Power Alarm Interrupt Pending Si3200 Power Alarm Interrupt Enable Q1/Q2 Power Alarm Threshold (discrete) Q1/Q2 Power Alarm Threshold (Si3200) Q3/Q4 Power Alarm Threshold Q5/Q6 Power Alarm Threshold Q1/Q2 Thermal LPF Pole Q3/Q4 Thermal LPF Pole Q5/Q6 Thermal LPF Pole Q1-Q6 Power Alarm Interrupt Pending Q71-Q6 Power Alarm Interrupt Enable Location PSUM IRQVEC3 IRQEN3 PTH12 PTH34 PTH56 PLPF12 PLPF34 PLPF56 IRQVEC3 IRQEN3 Register/RAM Bits PSUM[15:0] PQ1S PQ1E PTH12[15:0] PTH34[15:0] PTH56[15:0] PLPF12[15:3] PLPF34[15:3] PLPF56[15:3] Measurement Range 0 to 34.72 W N/A N/A 0 to 16.319 W 0 to 34.72 W 0 to 1.03 W 0 to 16.319 W Resolution 1059.6 W N/A N/A 498 W 1059.6 W 31.4 W 498 W
See "4.4.6. Power Filter and Alarms" See "4.4.6. Power Filter and Alarms" See "4.4.6. Power Filter and Alarms" TBD TBD N/A N/A
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4.5. Automatic Dual Battery Switching
The SI3232 and Si3200 provide the ability to switch between several user-provided battery supplies to aid thermal management. This method is required during the ringing to off-hook and on-hook to off-hook state transitions. During the on-hook operating state, the SI3232 must operate from the ringing battery supply in order to quickly provide the desired ringing signal when required. Once an off-hook condition has been detected, the SI3232 must transition to the lower battery supply (typically -24 V, in order to reduce power dissipation during the active state). The low current consumed by the SI3232 during the on-hook state results in very little power dissipation while being powered from the ringing battery supply, which can have an amplitude as high as 100 V depending on the desired ringing amplitude. The BATSEL pins serve to switch between the two battery voltages based on the operating state and the TIP-RING voltage. Figure 12 illustrates the chip connections required to implement an automatic dual battery switching scheme. When BATSEL is pulled low, the desired channel is powered from the VBLO supply. When BATSEL is pulled high, the VBHI source will supply power to the desired channel. The BATSEL pins for both channels are controlled using the BATSEL bit of the RLYCON register and should be programmed to automatically switch to the lower battery supply (VBLO) whenever an off-hook condition is sensed. Two thresholds are provided to enable battery switching with hysteresis. The BATHTH RAM location specifies the threshold at which the SI3232 will switch from the low battery, VBLO, to the high battery, VBHI, due to an off-hook to on-hook transition. The BATLTH RAM location specifies the threshold at which the SI3232 will switch from VBHI to VBLO due to a transition from the onhook or ringing state to the off-hook state or because the overhead during active off-hook mode is sufficient to feed the subscriber loop using a lower battery voltage. The low-pass filter coefficient is calculated using the equation below and is entered into the BATLPF RAM location. BATLPF = [(2f x 4096)/800] x 23 Where f = the desired cutoff frequency of the filter The programmable range of the filter is from 0 (blocks all signals) to 4000h (unfiltered). A typical value of 10 (0A10h) is sufficient to filter out any unwanted ac artifacts while allowing the dc information to pass through the filter. Table 17 provides the register and RAM locations used for programming the battery switching functions.
Table 17. Register and RAM Locations used for Battery Switching
Parameter High Battery Detect Threshold Low Battery Detect Threshold Ringing Battery Switch Battery Select Indicator Battery Switching LPF Register/RAM Mnemonic BATHTH BATLTH RLYCON RLYCON BATLPF Register/RAM Bits BATHTH[14:0] BATLTH[14:0] GPO BSEL BATLPF[15:3] Programmable Range 0 to 160.173 V* 0 to 160.173 V* Toggle Toggle 0 to 4000 Resolution (LSB Size) 628 mV (4.907 mV) 628 mV (4.907 mV) N/A N/A N/A
*Note: The usable range for BATHTH and BATLTH is limited to the VBHI voltage.
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SVBAT
Battery Sensing Circuit
Battery Logic Control
BATSEL
SI3232
806 k
40.2 k
BATSEL
Si3200 Linefeed Circuitry
VBLO VBATL VBAT
Battery Select Control
VBHI
VBATH
Figure 12. External Battery Switching Using the SI3232 and Si3200
When generating a high-voltage ringing amplitude using the Si3220, the power dissipated during the OHT state typically increases due to operating from the ringing battery supply in this mode. To reduce power, the SI3232/ Si3200 chipset provides the ability to accommodate up to three separate battery supplies by implementing a secondary battery switch using a few low-cost external components as illustrated in Figure 13. The SI3232's BATSEL pin is used to switch between the VBHI (typically -48 V) and VBLO (typically -24 V) rails using the switch internal to the Si3200. The SI3232's GPO pin is used along with the external transistor circuit to switch the VBRING rail (the ringing voltage battery rail) onto the Si3200's VBAT pin when ringing is enabled. The GPO signal is driven automatically by the ringing cadence provided that the RRAIL bit of the RLYCON register is set to 1 (signifying that a third battery rail is present).
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SI3232
R5
Si3200
0.1 F
R9 40.2 k Q1 R102 10 k Q2
GPO
SVBAT
BATSEL R101 CXT5401 402 k R103 CXT5551
806 k
VBAT VBATH VBATL BATSEL
D1
VBRING VBLO
0.1 F
VBHI
IN4003
Figure 13. Three-Battery Switching with SI3232
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Table 18. 3-Battery Switching Components
Component D1 Q1 Q2 R101 R102 R103 4.5.1. Loop Closure Detection Loop closure detection is required to accurately signal a terminal device going off-hook during the Active or OnHook Transmission linefeed states (forward or reverse polarity). The functional blocks required to implement a loop closure detector are shown in Figure 14, and the register set for detecting a loop closure event is provided in Table 19. The primary input to the system is the Loop Current Sense value provided by the voltage/ current/power monitoring circuitry and reported in the ILOOP RAM address. The loop current (ILOOP) is computed by the ISP using the equations shown below. Refer to Figure 11 on page 26 for the discrete bipolar transistor references used in the equation below (Q1, Q2, Q5 and Q6 - note that the Si3200 has corresponding MOS transistors). The same ILOOP equation applies to the discrete bipolar linefeed as well as the Si3200 linefeed device. The following equation is conditioned by the CMH status bit in register LCRRTP and by the linefeed state as indicated by the LFS field in the LINEFEED register.
I loop = I Q1 - I Q6 + I Q5 - I Q2 in TIP-OPEN or RING-OPEN I Q1 - I Q6 + I Q5 - I Q2 = --------------------------------------------------- in all other states 2
Value 200 V, 200 mA 100 V PNP 100 V NPN 1/10 W, 5% 10 k, 1/10 W, 5% 402 k, 1/10 W, 1%
Comments IN4003 or similar CXT5401 or similar CXT5551 or similar 2.4 k for VDD = 3.3 V 3.9 k for VDD = 5 V
The conditioning due to the CMH bit (LCRRTP Register) and LFS field (LINEFEED Register) states can be summarized as follows: IQ1 = 0 if (CMH = 1 AND (LFS = 1 OR LFS = 3)) IQ2 = 0 if (CMH = 1 AND (LFS = 5 OR LFS = 7)) The output of the Input Signal Processor is the input to a programmable digital low-pass filter, which can be used to remove unwanted ac signal components before threshold detection. The low-pass filter coefficient is calculated using the following equation and is entered into the LCRLPF RAM location. LCRLPF = [(2f x 4096)/800] x 23 Where f is the desired cutoff frequency of the filter. The programmable range of the filter is from 0h (blocks all signals) to 4000h (unfiltered). A typical value of 10 (0A10h) is sufficient to filter out any unwanted ac artifacts while allowing the dc information to pass through the filter. The output of the low-pass filter is compared to a programmable threshold, LCROFFHK. Hysteresis is enabled by programming a second threshold, LCRONHK, to detect the loop going to an OPEN or onhook state. The threshold comparator output feeds a programmable debounce filter. The output of the debounce filter remains in its present state unless the input remains in the opposite state for the entire period of time programmed by the loop-closure debounce interval, LCRDBI. There is also a loop-closure mask interval, LCRMASK, that is used to mask transitions caused when an internal ringing burst (no dc offset) ends in the presence of a high REN load. If the debounce interval has been satisfied, the LCR bit will be set to indicate that a valid loop closure has occurred.
If the CMHITH (RAM 36) threshold is exceeded, the CMH bit is 1, and IQ1 is forced to zero in the FORWARD-ACTIVE and TIP-OPEN states, or IQ2 is forced to zero in the REVERSE-ACTIVE and RINGOPEN states. The other currents in the equation are allowed to contribute normally to the ILOOP value.
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IQ1 IQ2 IQ5 IQ6
Input Signal Processor
ILOOP
Digital LPF
+ -
Loop Closure Mask
Debounce Filter
LCR
LCRLPF CMH LFS Loop Closure Threshold LOOPE LCROFFHK LCRONHK LCRMASK LCRDBI Interrupt Logic LOOPS
Figure 14. Loop Closure Detection Circuitry Table 19. Register and RAM Locations used for Loop Closure Detection
Parameter Register/ RAM Mnemonic
IRQVEC2 IRQEN2 LINEFEED LCRRTP LCRDBI ILOOP LCROFFHK LCRONHK LCRLPF LCRMASK
Register/RAM Bits
LOOPS LOOPE LFS[2:0] LCR LCRDBI[15:0] ILOOP[15:0] LCROFFHK[15:0] LCRONHK[15:0] LCRLPF[15:3] LCRMASK[15:0]
Programmable Range
Yes/No Yes/No Monitor only Monitor only 0 to 40.96 s 0 to 101.09 mA 0 to 101.09 mA2 0 to 101.09 mA2 0 to 4000h 0 to 40.96 s
LSB Size
N/A N/A N/A N/A 1.25 ms 3.097 A 3.097 A 3.097 A N/A 1.25 ms
Resolution
Loop Closure Interrupt Pending Loop Closure Interrupt Enable Linefeed Shadow Loop Closure Detect Status Loop Closure Detect Debounce Interval Loop Current Sense Loop Closure Threshold (on-hook to off-hook) Loop Closure Threshold (off-hook to on-hook) Loop Closure Filter Coefficient Loop Closure Mask Interval
N/A N/A N/A N/A 1.25 ms 500 A1 396.4 A 396.4 A N/A 1.25 ms
Notes: 1. ILOOP is a calculated value based on measured IQ1-IQ4 currents. The resulting effective resolution is approximately 500 A. 2. The usable range for LCRONHK and LCROFFHK is limited to 61 mA. Entering a value >61 mA disables threshold detection.
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4.5.2. Ground Key Detection Ground key detection detects an alerting signal from the terminal equipment during the tip open or ring open linefeed states. The functional blocks required to implement a ground key detector are shown in Figure 15, and the register set for detecting a ground key event is provided in Table 22 on page 36. The primary input to the system is the longitudinal current sense value provided by the voltage/current/power monitoring circuitry and reported in the ILONG RAM address. The ILONG value is produced in the ISP provided the LFS bits in the linefeed register indicate the device is in the tip open or ring open state. The longitudinal current (ILONG) is computed as shown in the following equation. Refer to Figure 11 on page 26 for the transistor references used in the equation (Q1, Q2, Q5 and Q6 - note that the Si3200 has corresponding MOS transistors). The same ILONG equation applies to the discrete bipolar linefeed as well as the Si3200 linefeed device.
I Q1 - I Q6 - I Q5 + I Q2 I LONG = --------------------------------------------------2
The output of the debounce filter remains in its present state unless the input remains in the opposite state for the entire period of time programmed by the loop closure debounce interval, LONGDBI. If the debounce interval is satisfied, the LONGHI bit is set to indicate that a valid ground key event has occurred. When the Si3220/25 detects a ground key event, the linefeed automatically transitions from the TIP-OPEN (or RING-OPEN) state to the FORWARD-ACTIVE (or REVERSE-ACTIVE) state. However, this automatic state transition is triggered by the LCR bit becoming active (i.e., =1), and not by the LONGHI bit. While ILONG is used to generate the LONGHI status bit, a transition from TIP-OPEN to the FORWARD-ACTIVE state (or from the RING-OPEN to the REVERSEACTIVE state) occurs when the RING terminal (or TIP terminal) is grounded and is based on the LCR bit and implicitly on exceeding the LCROFFHK threshold. As an example of ground key detection, suppose that the Si3220/25 has been programmed with the current values shown in Table 20.
The output of the ISP (ILONG) is the input to a programmable, digital low-pass filter, which removes unwanted ac signal components before threshold detection. The low-pass filter coefficient is calculated using the following equation and is entered into the LONGLPF RAM location:
( 2f x 4096 ) 3 LONGLPF = -------------------------------- x 2 800
Table 20. Settings for Ground Key Example
ILIM LCROFFHK LCRONHK LONGHITH LONGLOTH 21 mA 14 mA 10 mA 7 mA 5 mA
Where f = the desired cutoff frequency of the filter. The programmable range of the filter is from 0h (blocks all signals) to 4000h (unfiltered). A typical value of 10 (0A10h) is sufficient to filter out any unwanted ac artifacts while allowing the dc information to pass through the filter. The output of the low-pass filter is compared to the programmable threshold, LONGHITH. Hysteresis is enabled by programming a second threshold, LONGLOTH, to detect when the ground key is released. The threshold comparator output feeds a programmable debounce filter.
With the settings of Table 20, the behavior of ILOOP, ILONG, LCR, LONGHI, and CMHIGH is as shown in Table 21. The entries under "Loop State" indicate the condition of the loop, as determined by the equipment terminating the loop. The entries under "LINEFEED Setting" indicate the state initially selected by the host CPU (e.g., TIP-OPEN) and the automatic transition to the FORWARD-ACTIVE state due to a ground key event (when RING is connected to GND). The transition from state #2 to state #3 in Table 21 is the automatic transition from TIP-OPEN to FWD-ACTIVE in response to LCR = 1.
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Table 21. State Transitions During Ground Key Detection
# 1 2 3 4 5 Loop State LOOP OPEN RING-GND RING-GND LOOP CLOSURE LOOP OPEN LINEFEED State LFS = 3 (TIP-OPEN) LFS = 3 (TIP-OPEN) LFS = 1 (FWD-ACTIVE) LFS = 1 (FWD-ACTIVE) LFS = 1 (FWD-ACTIVE) ILOOP (mA) ILONG (mA) 0 22 22 21 0 0 -11 -11 0 0 LCR 0 1 1 1 0 LONGHI 0 1 1 0 0 CMHIGH 0 0 1 0 0
IQ1 IQ2 IQ5 IQ6 LONGLPF LFS Ground Key Threshold LONGE LONGHITH LONGLOTH LONGDBI Interrupt Logic LONGS Input Signal Processor ILONG Digital LPF + - Debounce Filter
LONGHI
Figure 15. Ground Key Detection Circuitry
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Table 22. Register and RAM Locations used for Ground Key Detection
Parameter Register/ RAM Mnemonic IRQVEC2 IRQEN2 LINEFEED LCRRTP LONGDBI ILONG LONGHITH LONGLOTH LONGLPF Register/RAM Bits LONGS LONGE LFS[2:0] LONGHI LONGDBI[15:0] ILONG[15:0] LONGHITH[15:0] LONGLOTH[15:0] LONGLPF[15:3] Programmable Range Yes/No Yes/No Monitor only Monitor only 0 to 40.96 s Monitor only 0 to 101.09 mA* 0 to 101.09 mA* 0 to 4000h 3.097 A 3.097 A N/A LSB Size Resolutio n N/A N/A N/A N/A 1.25 ms See Table 14 396.4 A 396.4 A N/A
Ground Key Interrupt Pending Ground Key Interrupt Enable Linefeed Shadow Ground Key Detect Status Ground Key Detect Debounce Interval Longitudinal Current Sense Ground Key Threshold (high) Ground Key Threshold (low) Ground Key Filter Coefficient
N/A N/A N/A N/A 1.25 ms
Note: The usable range for LONGHITH and LONGLOTH is limited to 16 mA. Setting a value >16 mA will disable threshold detection
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4.6. Ringing Generation
The SI3232 is designed to provide a balanced ringing waveform with or without dc offset. The ringing frequency, cadence, waveshape, and dc offset are all register-programmable. Using a balanced ringing scheme, the ringing signal is applied to both the TIP and the RING lines using ringing waveforms that are 180 out of phase with each other. The resulting ringing signal seen across TIP-RING is twice the amplitude of the ringing waveform on either the TIP or the RING line, which allows the ringing circuitry to withstand only half the total ringing amplitude seen across TIP-RING.
VRING RING
The ringing amplitude at the terminal equipment depends on the loop impedance as well as the load impedance in REN. The following equation can be used to determine the TIP-RING ringing amplitude required for a specific load and loop condition.
RLOOP ROUT
+
VRING
RLOAD
VTERM
-
SLIC
VTIP
VOFF TIP
Figure 17. Simplified Loop Circuit During Ringing
R LOAD V TERM = V RING x ---------------------------------------------------------------R LOAD + R LOOP + R OUT
where
GND VTIP V PK VOFF VCM
R LOOP = 0.09 per foot for 26 AWG wire R OUT = 320 7000 R LOAD = ------------------#REN
VRING VBATH
VOV
Figure 16. Balanced Ringing Waveform and Components
The purpose of an internal ringing scheme is to provide >40 Vrms into a 5 REN load at the terminal equipment using a user-provided ringing battery supply. The specific ringing supply voltage required depends on the ringing voltage desired.
When ringing longer loop lengths, adding a dc offset voltage is necessary to reliably detect a ring trip condition (off-hook phone). Adding dc offset to the ringing signal decreases the maximum possible ringing amplitude. Adding significant dc offset also increases the power dissipation in the Si3200 and may require additional airflow or a modified PCB layout to maintain acceptable operating temperatures. The SI3232 automatically applies and removes the ringing signal during VOC-crossing periods to reduce noise and crosstalk to adjacent lines. Table 23 provides a list of registers required for internal ringing generation.
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Table 23. Register and RAM Locations used for Ringing Generation
Parameter Ringing Waveform Ringing Active Timer Enable Ringing Inactive Timer Enable Ringing Oscillator Enable Monitor Ringing Oscillator Active Timer Ringing Oscillator Inactive Timer Linefeed Control (Initiates Ringing State) On-Hook Line Voltage Ringing Voltage Offset Ringing Frequency Ringing Amplitude Ringing Initial Phase Sinusoidal Trapezoid Ringing Overhead Voltage Ringing Speedup Timer 4.6.1. Internal Sinusoidal Ringing A sinusoidal ringing waveform is generated by using an on-chip digital tone generator. The tone generator used to generate ringing tones is a two-pole resonator with a programmable frequency and amplitude. Since ringing frequencies are low compared to the audio band signaling frequencies, the sinusoid is generated at a 1 kHz rate. The ringing generator is programmed via the RINGFREQ, RINGAMP, and RINGPHAS RAM locations. The equations are as follows:
2f coeff = cos ---------------------- 1000 Hz
Register/RAM Mnemonic RINGCON RINGCON RINGCON RINGCON RINGTALO/ RINGTAHI RINGTILO/ RINGTIHI LINEFEED VOC RINGOF RINGFRHI/ RINGFRLO RINGAMP
Register/RAM Bits TRAP TAEN TIEN RINGEN RINGTA[15:0] RINGTI[15:0] LF[2:0] VOC[15:0] RINGOF[15:0] RINGFRHI[14:3]/ RINGFRLO[14:3] RINGAMP[15:0]
Programmable Range Sinusoid/Trapezoid Enabled/Disabled Enabled/Disabled Enabled/Disabled 0 to 8.19 s 0 to 8.19 s 000 to 111 0 to 63.3 V 0 to 63.3 V 4 to 100 Hz 0 to 160.173 V
Resolution (LSB Size) N/A N/A N/A N/A 125 ms 125 ms N/A 1.005 V (4.907 mV) 1.005 V (4.907 mV)
628 mV (4.907 mV) N/A 31.25 s 1.005 V (4.907 mV) 1.25 ms
23
RINGPHAS VOVRING SPEEDUPR
RINGPHAS[15:0] VOVRING[15:0] SPEEDUPR[15:0]
N/A 0 to 1.024 s 0 to 63.3 V 0 to 40.96 s
RINGFREQ = coeff x 2
Desired V PK 15 1 1 - coeff RINGAMP = -- ----------------------- x ( 2 ) x ----------------------------------4 1 + coeff 160.173 V RINGPHAS = 0
For example, to generate a 60 Vrms (87 VPK), 20 Hz ringing signal, the equations are as follows:
220 coeff = cos ---------------------- = .99211 1000 Hz RINGFREQ = .99211 x ( 2 ) = 8322461 = 0x7EFD9D
23
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15 1 .00789 85 RINGAMP = -- -------------------- x ( 2 ) x -------------------- = 273 = 0x111 4 1.99211 160.173
RINGPHAS = 4 x 0.05 x 8000 = 1600 (0x0640) RINGAMP = 90/160.8 x (215) = 18340 (0x47A5) RINGFREQ = (2 x RINGAMP) (0.0153 x 8000) = 300 (0x012C) The time registers and interrupts described in the sinusoidal ring description also apply to the trapezoidal ring waveform.
In addition to the variable frequency and amplitude, there is a selectable dc offset (VOFF) that can be added to the waveform. The dc offset is defined in the RINGOF RAM location. The ringing generator has two timers which allow on/off cadence settings up to 8 s on/8 s off. In addition to controlling ringing cadence, these timers control the transition into and out of the ringing state. To initiate ringing, the user must program the RINGFREQ, RINGAMP, and RINGPHAS RAM addresses as well as the RINGTA, and RINGTI registers, and select the ringing waveshape and dc offset. Once this is done, the TAEN and TIEN bits are set as desired. Ringing state is invoked by a write to the linefeed register. At the expiration of RINGTA, the SI3232 turns off the ringing waveform and goes to the on-hook transmission state. At the expiration of RINGTI, ringing is initiated again. This process continues as long as the two timers are enabled and the linefeed register remains in the ringing state. 4.6.2. Internal Trapezoidal Ringing In addition to the traditional sinusoidal ringing waveform, the SI3232 can generate a trapezoidal ringing waveform similar to the one illustrated in Figure 19. The RINGFREQ, RINGAMP, and RINGPHAS RAM locations are used for programming the ringing wave shape as follows: RINGPHAS = 4 x Period x 8000 RINGAMP = (Desired V/160.8 V) x (215) RINGFREQ = (2 x RINGAMP) / (tRISE x 8000) RINGFREQ is a value that is added or subtracted from the waveform to ramp the signal up or down in a linear fashion. This value is a function of rise time, period, and amplitude, where rise time and period are related through the following equation for the crest factor of a trapezoidal waveform.
3 1t RISE = -- T 1 - ---------- 2 4 CF
4.7. Internal Unbalanced Ringing
The SI3232 also provides the ability to generate a traditional battery-backed unbalanced ringing waveform for ringing terminating devices that require a high dc content or for use in ground-start systems that cannot tolerate a ringing waveform on both the TIP and RING leads. The unbalanced ringing scheme applies the ringing signal to the RING lead; the TIP lead remains at the programmed VCM voltage that is very close to ground. A programmable dc offset can be preset to provide dc current for ring trip detection. Figure 18 illustrates the internal unbalanced ringing waveform.
VRING RING
SI3232
DC Offset TIP
GND VTIP DC Offset
VCM
VOFF
-80V VBATR
VRING
VOVRING
Figure 18. Internal Unbalanced Ringing
To enable unbalanced ringing, set the RINGUNB bit of the RINGCON register. As is the case with internal balanced ringing, the unbalanced ringing waveform is generated by using the on-chip ringing tone generator. The tone generator used to generate ringing tones is a two-pole resonator with programmable frequency and amplitude. Since ringing frequencies are low compared to the audio band signaling frequencies, the ringing waveform is generated at a 1 kHz rate. The ringing generator is programmed via the RINGAMP, RINGFREQ, and RINGPHAS registers. The RINGOF register is used to set the dc offset position around
where
1T = Period = ------------f RING CF = desired crest factor
So, for a 90 VPK, 20 Hz trapezoidal waveform with a crest factor of 1.3, the period is 0.05 s, and the rise time requirement is 0.015 s.
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which the RING lead oscillates. The dc offset is set at a dc point equal to VCM - (-80 V + VOFF), where VOFF is the value that is input into the RINGOF RAM location. Positive VOFF values cause the dc offset point to move closer to ground (lower dc offset), and negative VOFF values have the opposite effect. The dc offset can be set to any value; however, the ringing signal is clipped digitally if the dc offset is set to a value that is less than half the ringing amplitude. In general, the following equation must hold true to ensure the battery voltage is sufficient to provide the desired ringing amplitude: |VBATR| > |VRING,PK + (-80 V + VOFF) + VOVRING| It is possible to create reverse polarity unbalanced ringing waveforms (the TIP lead oscillates while the RING lead stays constant) by setting the UNBPOLR bit of the RINGCON register. In this mode, the polarity of VOFF must also be reversed (in normal ringing polarity, VOFF is subtracted from -80 V, and in reverse polarity, ringing VOFF is added to -80 V). 4.7.1. Ringing Coefficients The ringing coefficients are calculated in decimal for sinusoidal and trapezoidal waveforms. The RINGPHAS and RINGAMP hex values are decimal-to-hex conversions in 16-bit, 2's complement representations for their respective RAM locations. To obtain sinusoidal RINGFREQ RAM values, the RINGFREQ decimal number is converted to a 24-bit 2's complement value. The lower 12 bits are placed in RINGFRLO bits 14:3. RINGFRLO bits 15 and 2:0 are cleared to 0. The upper 12 bits are set in a similar manner in RINGFRHI, bits 13:3. RINGFRHI bit 14 is the sign bit and RINGFRHI bits 2:0 are cleared to 0. For example, the register values RINGFREQ = 0x7EFD9D are as follows: RINGFRHI = 0x3F78 RINGFRLO = 0x6CE8 To obtain trapezoidal RINGFREQ RAM values, the RINGFREQ decimal number is converted to an 8-bit, 2's complement value. This value is loaded into RINGFRHI. RINGFRLO is not used. for
VTIP-RING
V OFF T=1/freq t RISE time
Figure 19. Trapezoidal Ringing Waveform
4.7.2. Ringing DC Offset Voltage A dc offset voltage can be added to the SI3232's ac ringing waveform by programming the RINGOF RAM address to the appropriate setting. The value of RINGOF is calculated as follows:
V OFF 15 RINGOF = -------------- x 2 160.8
4.7.3. Linefeed Overhead Voltage Considerations During Ringing The ringing mode output impedance allows ringing operation without overhead voltage modification (VOVR = OV). If an offset of the ringing signal from the RING lead is desired, VOVR can be used for this purpose. 4.7.4. Ringing Power Considerations The total power consumption of the SI3232/Si3200 chipset using internal ringing generation is dependent on the VDD supply voltage, the desired ringing amplitude, the total loop impedance, and the ac load impedance (number of REN). The following equations can be used to approximate the total current required for each channel during ringing mode.
V RING,PK 2 -I DD,AVE = ---------------------- x -- + I DD,OH Z LOOP V RING,PK 2 -I BAT,AVE = ---------------------- x - Z LOOP
Where:
V RING,PK = V RING,RMS x 2 Z LOOP = R LOOP + R LOAD + R OUT 7000 R LOAD = ------------ (for North America) REN
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R LOOP = loop impedance R OUT = SI3232 ouput impedance = 320 I DD,OH = I DD overhead current = 12 mA
under any condition. Figure 20 illustrates the internal functional blocks that serve to correctly detect and process a ring trip event. The primary input to the system is the loop current sense (ILOOP) value provided by the loop monitoring circuitry and reported in the ILOOP RAM location register. This ILOOP register value is processed by the input signal processor block provided that the LFS bits in the Linefeed register value indicate the device is in the ringing state. The output of the input signal processor then feeds into a pair of programmable digital low-pass filters; one for the ac ring trip detection path and one for the dc path. The ac path also includes a fullwave rectifier block prior to the LPF block. The outputs of each low-pass filter block are then passed on to a programmable ring trip threshold (RTACTH for ac detection and RTDCTH for dc detection). Each threshold block output is then fed to a programmable debounce filter that ensures a valid ring trip event. The output of each debounce filter remains constant unless the input remains in the opposite state for the entire period of time set using the ac and dc ring trip debounce interval registers, RTACDB and RTDCDB, respectively. The outputs of both debounce filter blocks are then ORed together. If either the ac or the dc ring trip circuits indicate a valid ring trip event has occurred, the RTP bit is set. Either the ac or dc ring trip detection circuits can be disabled by setting the respective ring trip threshold sufficiently high so it will not trip under any condition. A ring trip interrupt is also generated if the RTRIPE bit has been enabled.
4.8. Ring Trip Detection
A ring trip event signals that the terminal equipment has transitioned to an off-hook condition after ringing has commenced, thus ensuring that the ringing signal is removed before normal speech begins. The SI3232 is designed to implement either an ac- or dc-based internal ring trip detection scheme or a combination of both schemes. This allows system-design flexibility for addressing varying loop lengths of different applications. An ac ring trip detection scheme cannot reliably detect an off-hook condition when sourcing longer loop lengths, as the 20 Hz ac impedance of an off-hook long loop is indistinguishable from a heavilyloaded (5 REN) short loop in the on-hook state. Because of this situation, a dc ring trip detection scheme is required when sourcing longer loop lengths. The SI3232 can implement either an ac- or dc-based ring trip detection scheme depending on the application. Table 25 on page 43 lists the registers that must be written or monitored to correctly detect a ring trip condition. The SI3232 provides the ability to process a ring trip event using only an ac-based detection scheme. Using this scheme eliminates the need for adding dc offset to the ringing signal, which reduces the total power dissipation during the ringing state and maximizes the available ringing amplitude. This scheme is only valid for shorter loop lengths, as it may not be possible to reliably detect a ring trip event if the off-hook line impedance overlaps the on-hook impedance at 20 Hz. The SI3232 also provides the ability to add a dc offset component to the ringing signal and detect a ring trip event by monitoring the dc loop current flowing once the terminal equipment transitions to the off-hook state. Although adding dc offset reduces the maximum available ringing amplitude (using the same ringing supply), this method is required to reliably detect a valid ring trip event when sourcing longer loop lengths. The dc offset can be programmed from 0 to 63.3 V in the RINGOF RAM address as required to produce adequate dc loop current in the off-hook state. Depending on the loop length and the ring trip method desired, the ac or dc ring trip detection circuits can be disabled by setting their respective ring trip thresholds (RTACTH or RTDCTH) sufficiently high so it will not trip
4.9. Ring Trip Timeout Counter
The Dual ProSLIC incorporates a ringtrip timeout counter, RTCOUNT, that monitors the status of the ringing control. When exiting ringing, the Dual ProSLIC will allow the ringtrip timeout counter amount of time (RTCOUNT x 1.25 ms/LSB) for the mode to switch to On-hook Transmission or Active. The mode that is being exited to is governed by whether the command to exit ringing is a ringing active timer expiration (on-hook transmission) or ringtrip/manual mode change (Active mode). The ringtrip timeout counter will assure ringing is exited within its time setting (RTCOUNT x 1.25 ms/LSB, typically 200 ms).
4.10. Ring Trip Debounce Interval
The ac and dc ring trip debounce intervals can be calculated based on the following equations: RTACDB = tdebounce (1600/RTPER) RTDCDB = tdebounce (1600/RTPER)
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4.11. Loop Closure Mask
The Dual ProSLIC implements a loop closure mask to ensure mode change between Ringing and Active or On-hook Transmission without causing an erroneous loop-closure detection. The loop-closure mask register, LCRMASK, should be set such that loop-closure detections are ignored for (LCRMASK x 1.25 ms/LSB)
RTACTH
amount of time. The programmed time is set to mask detection of transitional currents that occur when exiting the ringing mode while driving a reactive load (i.e., 5 REN). A typical setting is 80 ms (LCRMASK = 0x40).
LFS
AC Ring Trip Threshold
_
ILOOP Input Signal Processor Digital LPF
+
Debounce Filter_AC
RTP
RTPER
RTACDB
Interrupt Logic
RTRIPS
Digital LPF
+ _
DC Ring Trip Threshold
RTRIPE Debounce Filter_DC
RTDCDB
RTDCTH
Figure 20. Ring Trip Detect Processing Circuitry
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Table 24. Recommended Ring Trip Detection Values1
Ringing Frequency 16-32 Hz DC Offset Added? Yes No 33-60 Hz Yes No RTPER 800/fRING 800/fRING 2(800/fRING) 2(800/fRING) RTACTH 221 x RTPER 1.59 x VRING,PK x RTPER 221 x RTPER 1.59 x VRING,PK x RTPER RTDCTH 0.577(RTPER x VOFF) 32767 0.577(RTPER x VOFF) 32767 See Note 2 RTACDB/ RTDCDB
Notes: 1. All calculated values should be rounded to the nearest integer. 2. Refer to Ring Trip Debounce Interval for RTACDB and RTDCDB equations.
Table 25. Register and RAM Locations for Ring Trip Detection
Parameter Ring Trip Interrupt Pending Ring Trip Interrupt Enable AC Ring Trip Threshold DC Ring Trip Threshold Ring Trip Sample Period Linefeed Shadow (monitor only) Ring Trip Detect Status (monitor only) AC Ring Trip Detect Debounce Interval DC Ring Trip Detect Debounce Interval Loop Current Sense (monitor only) Register/RAM Mnemonic IRQVEC2 IRQEN2 RTACTH RTDCTH RTPER LINEFEED LCRRPT RTACDB RTDCDB ILOOP Register/ RAM Bits RTRIPS RTRIPE RTACTH[15:0] RTDCTH[15:0] RTPER[15:0] LFS[2:0] RTP RTACDB[15:0] RTDCDB[15:0] ILOOP[15:0] Programmable Range Yes/No Enabled/Disabled See Table 24 See Table 24 See Table 24 N/A N/A 0 to 40.96 s 0 to 40.96 s 0 to 101.09 mA N/A N/A 1.25 ms 1.25 ms See Table 14 Resolution N/A N/A
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4.12. Relay Driver Considerations
The SI3232 includes a general-purpose driver output for each channel (GPOa, GPOb) to drive external test relays. In most applications, the relay can be driven directly from the SI3232 with no external relay drive circuitry required. Figure 21 illustrates the internal relay driver circuitry using a 3 V relay.
VDD SI3232 3 V/5 V Relay (polarized or non-polarized) Relay Driver Logic VCC
VDD SI3232 Polarized relay IDRV GPOa GPOb Q1 RDRV VCC
Figure 22. Driving Relays with VCC > VDD
GPOa/b
The maximum allowable RDRV value can be calculated using the following equation:
MaxR DRV =
GND
Figure 21. SI3232 Internal Relay Drive Circuitry The internal driver logic and drive circuitry is powered from the same 3.3 V supply as the chip's main supply (VDD1-VDD4 pins). When operating external relays from a VCC supply that is equal to the chip's VDD supply, an internal diode network provides protection against overvoltage conditions caused by flyback spikes when the relay is opened. Only 3 V relays may be used in the configuration shown in Figure 21, and either polarized or non-polarized relays are acceptable provided both VCC and VDD are powered by a 3.3 V supply. The input impedance, RIN, of the relay driver pins is a constant 11 while sinking less than the maximum rated 85 mA into the pin. If the desired operating voltage of the relay, VCC, is higher than the SI3232's VDD supply voltage, an external drive circuit is required to eliminate leakage from VCC to VDD through the internal protection diode. In this configuration, a polarized relay is recommended to provide optimal overvoltage protection with minimal external components. Figure 22 illustrates the required external drive circuit, and Table 26 provides recommended values for RDRV for typical relay characteristics and VCC supplies. The output impedance, ROUT, of the relay driver pins is a constant 63 while sourcing less than the maximum rated 28 mA out of the pin.
( V DD,MIN - 0.6 V ) ( R RELAY ) ( Q1,MIN ) ------------------------------------------------------------------------------------------------ - R SOURCE V CC,MAX - 0.3 V
where Q1,MIN ~ 30 for a 2N2222
Table 26. Recommended RDRV Values
ProSLIC VDD 3.3 V 5% 3.3 V 5% 3.3 V 5% 3.3 V 5% 3.3 V 5% Relay VCC 3.3 V 5% 5V 5% 12 V 10% 24 V 10% 48 V 10% Relay RCOIL 64 178 1028 2880 7680 Maximum RDRV Not Required 2718 6037 8364 11092 Recommended 5% Value -- 2.7 k 5.6 k 8.2 k 11 k
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4.12.1. Polarity Reversal The SI3232 supports polarity reversal for messagewaiting functionality as well as various signaling modes. The ramp rate can be programmed for a smooth transition or an abrupt transition to accommodate different application requirements. A wink function is also provided for special equipment that responds to a smooth ramp to VOC = 0 V. Table 27 illustrates the register bits required to program the polarity-reversal modes. An immediate reversal (hard reversal) of the line polarity is achieved by setting the Linefeed register to the opposite polarity. For example, a transition from Forward Active mode to Reverse Active mode is achieved by changing LF[2:0] from 001 to 101. Polarity reversal can also be accommodated in the OHT and ground-start modes. The POLREV bit is a read-only bit that reflects whether the device is in polarity reversal mode. A smooth polarity reversal is achieved by setting the PREN bit to 1 and setting the RAMP bit to 0 or 1 depending on the desired ramp rate (see Table 27). Polarity reversal is then accomplished by toggling the linefeed register from forward to reverse modes as desired. A wink function is used to slowly ramp down the TIPRING voltage (VOC) to 1 followed by a return to the original VOC value (set in the VOC RAM 0 location). This scheme is used to light a message-waiting lamp in certain handsets. To enable this function, no change to the linefeed register is necessary. Instead, the user must set the VOCZERO bit to 1 to cause the TIP-RING voltage to collapse to 0 V at the rate programmed by the RAMP bit. Setting the VOCZERO bit back to 0 causes the TIP-RING voltage to return to its normal setting. A software timer provided by the user can automate the cadence of the wink function. Figure 23 illustrates the wink function.
Table 27. Register and RAM Locations used for Polarity Reversal
Parameter Linefeed Polarity Reversal Status Wink Function (Smooth transition to Voc = 0 V) Smooth Polarity Reversal Enable Smooth Polarity Reversal Ramp Rate Programmable Range See Table 12 Read only 1 = Ramp to 0 V 0 = Return to previous VOC 0 = Disabled 1 = Enabled 0 = 1 V/125 s 1 = 2 V/125 s Register/RAM Bits LF[2:0] POLREV VOCZERO PREN RAMP Location LINEFEED POLREV POLREV POLREV POLREV
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Set VOCZERO bit to 1 0 0 10 20 30 Set VOCZERO bit to 0 40 50 60 70 80
Vcm
Time (ms) VTIP
-10
-20 2V/125 s slope set by RAMP bit -30
Voc
-40
-50
Vov
VRING VBAT
V TIP/RING (V)
Figure 23. Wink Function with Programmable Ramp Rate
4.13. Two-Wire Impedance Synthesis
Two-wire impedance synthesis is performed on-chip to optimally match the output impedance of the SI3232 to the impedance of the subscriber loop, thus minimizing the receive path signal reflected back onto the transmit path. The SI3232 provides on-chip selectable analog two-wire impedances to meet return loss requirements. The subscriber loop varies with any series impedance due to protection devices placed between the Si3200 outputs and the TIP/RING pair according to the following equation:
Z T = 2R PROT + R A
TIP
RPROT Si3200
ZL
ZT
SI3232
RING
RPROT
Figure 24. Two-Wire Impedance Simplified Circuit
4.13.1. Transhybrid Balance Filter The SI3232 is intended to be used with DSP-based codecs that provide the transhybrid balance function. No transhybrid capability exists in the SI3232. 4.13.2. Pulse Metering Generation The SI3232 offers an internal tone generator suitable for generating tones above the audio frequency band. This oscillator is provided for the generation of billing tones which are typically 12 kHz or 16 kHz. The equations for calculating the pulse metering coefficients are as follows: Coeff = cos (2f/64000 Hz) PMFREQ = coeff (214 - 1)
*
Where:
ZT is the termination impedance presented to the TIP/RING pair RPROT is the series resistance caused by protection devices RA is the analog portion of the selected impedance
Therefore, the user must also consider the value of RPROT when programming the on-chip analog impedance. The SI3232's analog impedance synthesis scheme is sufficient for many short loop applications. If a unique complex ac impedance is required, the SI3232's impedance scheme must be augmented or replaced by a DSP-based impedance generator. To turn off the analog impedance coefficients (RS, ZP, and ZZ), set the ZSDIS bit of the ZZ register to 0.
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Desired V PK 15 1 1 - coeff PMAMPL = -- ----------------------- x ( 2 - 1 ) x ----------------------------------------Full Scale V PK 4 1 + coeff
where Full Scale VPK = 0.5 V. The pulse metering oscillator has a volume envelope (linear ramp) on the on/off transitions of the oscillator. The ramp is controlled by the value entered into the PMRAMP RAM address, and the sinusoidal generator output is multiplied by this volume before being sent to the pulse metering DAC. The volume value is incremented by the value in PMRAMP at an 8 kHz rate. The volume ramps from 0 to 7FFF in increments of
PMRAMP, thus allowing the value of PMRAMP to set the slope of the ramp. The clip detector stops the ramp once the signal seen at the transmit path exceeds the amplitude threshold set by PMAMPTH, thus providing an automatic gain control (AGC) function to prevent the audio signal from clipping. When the pulse metering signal is turned off, the volume ramps down to 0 by decrementing according to the value of PMRAMP. Figure 24 illustrates the functional blocks involved in pulse-metering generation, and Table 28 presents the register and RAM locations required that must be set to generate pulse-metering signals.
Table 28. Register and RAM Locations Used for Pulse Metering Generation
Parameter Register/RAM Mnemonic Register/RAM Bits Description / Range (LSB Size)
Pulse-Metering Frequency Coefficient Pulse-Metering Amplitude Coefficient Pulse-Metering Attack/Decay Ramp Rate Pulse-Metering Active Timer Pulse-Metering Inactive Timer Pulse-Metering, Control Interrupt
PMFREQ PMAMPL PMRAMP PMTALO/PMTAHI PMTILO/PMTIHI IRQVEC1, IRQEN1
PMFREQ[15:3] PMAMPL[15:0] PMRAMP[15:0] PULSETA[15:0] PULSETI[15:0] PULSTAE, PULSTIE, PULSTAS, PULSTIS PMAMPTH[15:0] ENSYNC TAEN1 TIEN1 PULSE1
Sets oscillator frequency Sets oscillator amplitude 0 to PMAMPL (full amplitude) 0 to 8.19 s (125 s) 0 to 8.19 s (125 s) Interrupt status and control registers
Pulse-Metering AGC Amplitude Threshold PM Waveform Present PM Active Timer Enable PM Inactive Timer Enable Pulse-Metering Enable
PMAMPTH PMCON PMCON PMCON PMCON
0 to 500 mV Indicates Signal Present Enable/disable Enable/disable Enable/disable
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To VTX outputs
12/16 kHz Bandpass
Peak Detector - IBUF ZA
+
PMAMPTH +
From VRX inputs
PMRAMP Pulse Metering DAC
+ -
+
+
Pulse Metering Oscillator
Volume
Clip Logic 7FFF or 0
8 kHz
Figure 25. Pulse Metering Generation Block Diagram
4.14. Audio Path Processing
The SI3232 is designed to connect directly to integrated access device (IAD) chipsets, such as the Broadcom BCM3341, as well as other standard codecs that use a differential audio interface. Figure 3 on page 15 illustrates the simplified block diagram for the SI3232.
4.14.1. Transmit Path
Table 29. ATX Attenuation Stage Settings
ATXMUT E Setting ATX Setting Typical TX Path Gain
1 0 0
X 0 1
Mute (no output) -1.584 dB (G = 10/12) -4.682 dB (G = 7/12)
In the transmit path, the analog signal fed by the external ac-coupling capacitors, C1 and C2, is amplified by the analog transmit amplifier, ATX, prior to the differential analog output to the A/D converter in the external codec. The ATX stage can be used to add 3 dB of attenuation by programming the ATX bit of the AUDGAIN register. A mute function is also available by setting the ATXMUTE bit of the AUDGAIN register to 1. The main role of the ATX stage is to attenuate incoming signals to best match the input scale of the external A/D converter to maximize signal-to-noise ratio. The resulting gain levels using the ATX stage are summarized in Table 29. All settings assume a 0 dBm0 TIP-RING audio input signal with the audio TX level measured differentially at VTXPa-VTXNa (for channel a) or VTXPb-VTXNb (for channel b).
4.14.2. Receive Path
In the receive path, the incoming audio signal from the D/A converter in the external codec is passed through an ARX stage where the user can attenuate audio signals in the analog domain prior to transmission to TIP/RING. Settings of 0, -3, and -6 dB are available by programming the ARX[1:0] bits of the AUDGAIN register to the appropriate settings. A mute function is also available by setting the ARXMUTE bit of the AUDGAIN register to 1. When not muted, the resulting analog signal is applied at the input of the transconductance amplifier, Gm, which drives the offchip current buffer, IBUF.
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The resulting gain levels using the ARX stage are summarized in Table 30. All settings assume an external codec with 475 per leg of source impedance driving the RX inputs differentially at VRXPa-VRXNa (for channel a) or VRXPb-VRXNb (for channel b) to achieve a 0 dBm0 TIP-RING audio output signal. or update of the PLL-MULT register. The PLL lock process begins immediately after the RESET pin is pulled high and will take approximately 5 ms to achieve lock after RESET is released with stable PCLK and FSYNC. However, the settling time depends on the PCLK frequency and can be predicted based on the following equation: tSETTLE = 64 / fPCLK
Note: Therefore, the RESET pin must be held low during powerup and should only be released when both PCLK and FSYNC signals are known to be stable.
Table 30. ARX Attenuation Stage Settings
ARXMUTE Setting ARX[1:0] Setting Typical TX Path Gain
1 0 0 0 0
xx 00 01 10 11
Mute (no T-R output) 0 dB (G = 1) -3.52 dB (G = 2/3) -6.02 dB (G = 1/2) Reserved. Do not use.
4.15.1. Interrupt Logic
The SI3232 is capable of generating interrupts for the following events: Loop current/ring ground detected. Ground key detected. Ring trip detected. Power alarm. Ringing active timer expired. Ringing inactive timer expired. Pulse metering active timer expired. Pulse metering inactive timer expired. RAM address access complete. The interface to the interrupt logic consists of six registers. Three interrupt status registers (IRQ0-IRQ3) contain one bit for each of the above interrupt functions. These bits are set when an interrupt is pending for the associated resource. Three interrupt mask registers (IRQEN1-IRQEN3) also contain one bit for each interrupt function. In the case of the interrupt mask registers, the bits are active high. Refer to the appropriate functional description text for operational details of the interrupt functions.
4.15. System Clock Generation
The SI3232 generates the necessary internal clock frequencies from the PCLK input. PCLK must be synchronous to the 8 kHz FSYNC clock and run at one of the following rates: 256 kHz, 512 kHz, 786 kHz, 1.024 MHz, 1.536 MHz, 1.544 MHz, 2.048 MHz, 4.096 MHz, or 8.192 MHz. The ratio of the PCLK rate to the FSYNC rate is determined by a counter clocked by PCLK. The 3-bit ratio information is automatically transferred into an internal register, PLL_MULT, following a device reset. PLL_MULT is used to control the internal PLL, which multiplies PCLK as needed to generate the rate required to run the internal filters and other circuitry. The PLL clock synthesizer settles quickly after powerup
PCLK
PFD
VCO
/2
/2
28.672 MHz
DIV M
RESET
PLL_MULT
Figure 26. PLL Frequency Synthesizer
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When a resource reaches an interrupt condition, it signals an interrupt to the interrupt control block. The interrupt control block then sets the associated bit in the interrupt status register if the mask bit for that interrupt is set. The INT pin is a NOR of the bits of the interrupt status registers. Therefore, if a bit in the interrupt status registers is asserted, IRQ asserts low. Upon receiving the interrupt, the interrupt handler should read interrupt status registers to determine which resource is requesting service. All interrupt bits in the interrupt status registers, IRQ0-IRQ3, are cleared following a register read operation. While the interrupt status registers are non-zero, the INT pin remains asserted. There are a number of variations of usage on this fourwire interface as follows:
Continuous clocking. During continuous clocking, the data transfers are controlled by the assertion of the CSB pin. CSB must be asserted before the falling edge of SCLK on which the first bit of data is expected during a read cycle and must remain low for the duration of the 8-bit transfer (command/ address or data), going high after the last rising of SCLK after the transfer. Clock only during transfer. In this mode, the clock cycles only during the actual byte transfers. Each byte transfer will consist of eight clock cycles in a return to 1 format. SDI/SDO wired operation. Independent of the clocking options described, SDI and SDO can be treated as two separate lines or wired together if the master is capable of tri-stating its output during the data byte transfer of a read operation. Soft reset. The SPI state machine resets whenever CSB is asserted during an operation on an SCLK cycle that is not a multiple of eight. This provides a mechanism for the controller to force the state machine to a known state in the case where the controller and the device appear to be out of synchronization. The control byte has the following structure and is presented on the SDI pin MSB first. The bits are defined in Table 31.
4.16. SPI Control Interface
The SI3232 has a 4-wire serial peripheral interface (SPI) control bus modeled after commonly-available micro-controller and serial peripheral devices. The interface consists of a clock (SCLK), chip select (CSB), serial data input (SDI), and serial data output (SDO). In addition, the SI3232 includes a serial data through output (SDI_THRU) to support daisy chain operation of up to eight devices (up to sixteen channels). The device can operate with both 8-bit and 16-bit SPI controllers. Each SPI operation consists of a control byte, an address byte (of which only the seven LSBs are used internally), and either one or two data bytes depending on the width of the controller and whether the access is to a direct or indirect register. Bytes are always transmitted MSB first. 7 BRDCST 6 R/W 5 4
3 CID[0]
2 CID[1]
1 CID[2]
0 CID[3]
REG/RAM Reserved
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Refer to "2. Typical Application Schematic" on page 17. The pulldown resistor on the SDO pin is required to allow this node to discharge after a logic high state to a tri-state condition. The discharge occurs while SDO is tri-stated during an 8 kHz transmission frame. The value of the pulldown resistor depends on the capacitance seen on the SDO pin. In the case of using a single SI3232, the value of the pulldown resistor is 39 k. This assumes a 5 pF SDO pin capacitance and about a 15 pF load on the SDO pin. For applications using multiple SI3232 devices or different capacitive loads on the SDO pin, a different pulldown resistance needs to be calculated. The following design procedure is an example for calculating the pulldown resistor on the SDO pin in a system using eight SI3232 devices. A pullup resistor is not allowed on the SDO pin.
1. The SDO node must discharge and remain discharged for 244 ns. The discharge occurs during the Hi-Z state; therefore, the time to discharge is equal to the time in Hi-Z time minus the 244 ns.
4. We want to discharge and remain discharged for 244 ns. Therefore, the discharge time is: 992 ns - 244 ns = 748 ns 5. To allow for some margin, let's discharge in 85% of this time. 748nS x 85% = 635.8 ns 6. Determine capacitive load on the SDO pin: a.Allow 5 pF for each Si3220 SDO pin that connected together. b.Allow ~2 pF/inch (~0.8 pF/cm) for PCB trace. c.Include the load capacitance of the host IC input. 7. For a system with eight Si3220 devices, the capacitance seen on the SDO pin would be: a.8 x 5 pF for each Si3220 = 40 pF b.Assume 5 inch of PCB trace: 5inch x 2 pF/ inch = 10 pF c.Host IC input of 5 pF d.Total capacitance is 55 pF 8. Using the equation t = RC, allowing five time constants to decay, and solving for R a.R = t / 5C = 635.8 ns / (5 x 55 pF) b.R = 2.3 k So, R must be less than 2.3 k to allow the node to discharge.
2. Allow five time constants for discharge where the time constant, t = RC 3. SDO will be in Hi-Z while SDI is sending control and address which are each 8 bits. Using the maximum SCLK frequency of 16.13 MHz, the SDO will be in Hi-Z for 16 / 16.13 MHz = 992 ns. 7
Table 31. SPI Control Interface
BRDCST Indicates a broadcast operation that is intended for all devices in the daisy chain. This is only valid for write operations since it would cause contention on the SDO pin during a read. R/W
Read/Write Bit. 0 = Write operation. 1 = Read operation.
6
5
REG/RAM Register/RAM Access. 0 = RAM access. 1 = Register access. Reserved CID[3:0] This field indicates the channel that is targeted by the operation. The 4-bit channel value is provided LSB first. The devices reside on the daisy chain such that device 0 is nearest to the controller, and device 15 is furthest down the SDI/SDU_THRU chain. (See Figure 26.) As the CID information propagates down the daisy chain, each channel decrements the CID by 1. The SDI nodes between devices will reflect a decrement of 2 per device since each device contains two channels. The device receiving a value of 0 in the CID field will respond to the SPI transaction. (See Figure 27.) If a broadcast to all devices connected to the chain is requested, the CID will not decrement. In this case, the same 8-bit or 16-bit data is presented to all channels regardless of the CID values.
4 3:0
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SI3232
4.17. SI3232 RAM and Register Space
The SI3232 is a highly-programmable telephone linecard solution that uses internal registers and RAM to program operational parameters and modes. The Register Summary and RAM Summary are compressed listings for single-entry quick reference. The Register Descriptions and RAM Descriptions give detailed information of each register or RAM location's bits. All RAM locations are cleared upon a hardware reset. All RAM locations that are listed as "INIT" must be initialized to a meaningful value for proper functionality. Bit 4 of the MSTRSTAT register indicates the clearing process is finished. This bit should be checked before initializing the RAM space. Accessing register and RAM space is performed through the SPI. Register space is accessed by using the standard three-byte access as described in the next section. Bit 5 of the control byte specifies register access when set to a 1. All register space is comprised of 8-bit data.
4.17.1. RAM Access by Pipeline
RAMDATLO and RAMDATHI registers. To write a RAM location in the SI3232, check for register RAMSTAT (bit 0) to indicate the previous access is completed and RAM is ready (0); then, write the 16 bits of RAM data to the RAMDATLO, RAMDATHI. Finally, write the RAM address to the RAMADDR register.
4.17.3. Chip Select
For register or RAM space access, there are three ways to use chip select: byte length, 16-bit length, and access duration length. The byte length method releases chip select after every 8 bits of communication with the SI3232. The time between chip select assertions must be at least 220 ns. The 16-bit length chip select method is similar to the byte length method except that 16-bits are communicated with the SI3232. This means that SI3232 communication consists of a control byte, address byte for one 16-bit access, and two data bytes for a second 16-bit access. In a single data byte communication (control byte, address byte, data byte), the data byte should be loaded into either the high byte or both bytes of the second 16-bit access for a write. The 8-bit data exists in the high and low byte of a 16-bit access for a read. The time between chip select assertion must be at least 220 ns. Access duration length allows chip select to be pulled low for the length of a number of SI3232 accesses. There are two very specific rules for this type of communication. One rule is that the SCLK must be of a frequency that is less than 1/2x220 ns (<2.25 MHz). The second rule is that access must be done in a 16-bit modulus. This 16-bit modulus follows the same rules as described above for 16-bit length access where 8-bit data is concerned.
4.17.4. Protected Register Bits
Ram space can be accessed by two different methods. One method is a pipeline method that employs a 4-byte access plus a RAM status check. The control byte for the pipeline method has bit 6 cleared to 0 to indicate a RAM access. The control byte is followed by the RAM address byte, then the two data bytes. Reading RAM in the pipeline method requires "priming" the data. First, check for register RAMSTAT, bit 0, to indicate the previous access is complete and RAM is ready (0). Then, perform the 4-byte RAM access. The first read will yield unusable data. The data read on the subsequent read access is the data for the previous address read. A final address read yields the last previously-requested data. The RAM-ready information (RAMSTAT) must be read before every RAM access. To write a RAM location, check for register RAMSTAT, bit 0, to indicate the previous access is complete and RAM is ready (0). Then, write the RAM address and data in the 4-byte method. A write to RAM location requires "priming" the data with subsequent accesses.
4.17.2. RAM Access by Register
The SI3232 has protected register bits that are meant to retain the integrity of the SI3232 circuit in the event of unintentional software register access. To access the user-protected bits, write the following sequence of data bytes to register address 87 (0x57): 0x02 0x10 0x12 0x00 Following the modification of any protected bit, the same sequence should be immediately written to place these bits into their protected state. Protected bits exist in registers SBIAS and THERM.
An alternative method to access RAM space utilizes three registers in sequence and monitors RAMSTAT register, bit 0. These three registers are RAMADDR, RAMDATLO, and RAMDATHI. To read a RAM location in the SI3232, check for register RAMSTAT (bit 0) to indicate the previous access is complete and RAM is ready (0). Then, write the RAM address to RAMADDR. Wait until RAMSTAT (bit 0) is a 1; then, the 16 bits of data can be read from the
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SDI0
SDO
SDI
CPU
CS SDI
SPI Clock
CS SDO
Channel 0
SDI1
SI3232 #1
Channel 1
SCLK SDITHRU SDI2 SDI
CS SDO
Channel 2
SDI3
SI3232 #2
Channel 3
SCLK SDITHRU SDI4
SDI14 SDI
CS SDO
Channel 14
SDI15
SI3232 #8
Channel 15
SCLK SDITHRU
Figure 27. SPI Daisy Chain Control Architecture
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In Figure 28, the CID field is 0. As this field is decremented (LSB to MSB order), the value decrements for each SDI down the line. The BRDCST, R/W, and REG/RAM bits remain unchanged as the control word passes through the entire chain. The odd SDIs are internal to the device and represent the SDI to SDI_THRU connection between channels of the same device. A unique CID is presented to each channel, and the channel receiving a CID value of 0 is the target of the operation (channel 0 in this case). The last line of Figure 28 illustrates that in broadcast mode, all bits are passed through the chain without permutation.
SPI Control Word
BRDCST SDI0 SDI1 (Internal) SDI2 SDI3 (Internal) 0 0 0 0 R/W A A A A REG/RAM B B B B Reserved C C C C CID[0] 0 1 0 1 CID[1] 0 1 1 0 CID[2] 0 1 1 1 CID[3] 0 1 1 1
SDI 0-15 SDI15
0 0
A A
B B
C C
0 1
1 0
0 0
0 0
SDI0-15
1
A
B
C
D
E
F
G
Figure 28. Sample SPI Control Word to Address Channel 0
CS SCLK SDI SDO CONTROL ADDRESS DATA [7:0] Hi-Z
Figure 29. Register Write Operation via an 8-Bit SPI Port
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Figures 29 and 30 illustrate WRITE and READ operations to registers via an 8-bit SPI controller. These operations are each performed as a 3-byte transfer. CS is asserted between each byte. It is necessary for CS to be asserted before the first falling edge of SCLK after the DATA byte to indicate to the state machine that only one byte should be transferred. The state of SDI is a "don't care" during the DATA byte of a read operation. Figures 31 and 32 illustrate WRITE and READ operation to registers via a 16-bit SPI controller. These operations require a 4-byte transfer arranged as two 16-bit words. The absence of CS going high after the eighth bit of data indicates to the SPI state machine that eight more SCLK pulses will follow to complete the operation. In the case of a WRITE operation, the last eight bits are ignored. In the case of a read operation, the 8-bit data value is repeated so that the data can be captured during the last half of a data transfer if so desired by the controller. During register accesses, the CONTROL, ADDRESS, and DATA are captured in the SPI module. At the completion of the ADDRESS byte of a READ access, the contents of the addressed register are moved into the data register in the SPI. At the completion of the DATA byte of a WRITE access, the data is transferred from the SPI to the addressed register location.
CS SCLK SDI SDO CONTROL ADDRESS XXXXXXXX Data [7:0]
Figure 30. Register Read Operation via an 8-Bit SPI Port
CS SCLK SDI SDO CONTROL ADDRESS Data [7:0]
XXXXXXXX
Hi - Z
Figure 31. Register Write Operation via a 16-Bit SPI Port
CS SCLK SDI SDO CONTROL ADDRESS
XXXXXXXX XXXXXXXX
Data [7:0]
Data [7:0]
Same byte repeated twice.
Figure 32. Register Read Operation via a 16-Bit SPI Port
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Figures 33-36 illustrate the various cycles for accessing RAM address locations. RAM addresses are 16-bit entities; therefore the accesses always require four bytes.
CS SCLK SDI SDO CONTROL ADDRESS DATA [15:8] DATA [7:0] Hi-Z
Figure 33. RAM Write Operation via an 8-Bit SPI Port
CS SCLK SDI SDO xxxxxxxx DATA [15:8] xxxxxxxx DATA [7:0]
Figure 34. RAM Read Operation via an 8-Bit SPI Port
CS SCLK SDI SDO CONTROL ADDRESS Data [15:8] Data [7:0] Hi - Z
Figure 35. RAM Write Operation via a 16-Bit SPI Port
CS SCLK SDI SDO CONTROL ADDRESS
xxxxxxxxxxxxxxxx
Data [15:8]
Data [7:0]
Figure 36. RAM Read Operation via a 16-Bit SPI Port
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During RAM address accesses, CONTROL, ADDRESS, and DATA are captured in the SPI module. At the completion of the ADDRESS byte of a READ access, the contents of the channel-based data buffer are moved into the data register in the SPI for shifting out during the DATA portion of the SPI transfer. This is the data loaded into the data buffer in response to the previous RAM address read request. Therefore, there is a one-deep pipeline nature to RAM address READ operations. At the completion of the DATA portion of the READ cycle, the ADDRESS is transferred to the channel-based address buffer, and a RAM access request is logged for that channel. The RAMSTAT bit in each channel can be polled to monitor the status of RAM address accesses that are serviced twice per sample period at dedicated windows in the DSP algorithm. There is also a RAM access interrupt in each channel which, when enabled, indicates that the pending RAM access request has been serviced. For a RAM WRITE access, the ADDRESS and DATA is transferred from the SPI registers to the address and data buffers in the appropriate channel. The RAM WRITE request is then logged. As for READ operations, the status of the pending request can be monitored by either polling the RAMSTAT bit for the channel or enabling the RAM access interrupt for the channel. By keeping the address and data buffers as well as the RAMSTAT register on a per-channel basis, RAM address accesses can be scheduled for both channels without interface.
4.18.2. Line Test and Diagnostics
The SI3232 provides a variety of diagnostics tools that facilitate remote fault detection and parametric diagnostics on the TIP/RING pair as well as line card functionality verification. The SI3232 can generate dc line currents and voltages as well as measure all resulting line voltage and current levels on TIP, RING, or across the TIP/RING pair. When used in conjunction with an external codec that can generate discrete audio tones and discriminate certain audio frequency bands, the SI3232 can provide a vehicle to allow remote diagnostics on the subscriber loop and the line card. All parameters measured by the SI3232 are stored in registers for further processing by the codec and DSP, and all dc generation tools are register-programmable to allow a software-configurable remote diagnostic system. The SI3232's signal generation and measurement tools are summarized in Table 32. The accompanying text describes the methodology that can be used to develop a fully-programmable test suite to facilitate remote diagnostics.
ATX Mute +
To off-chip ADC
4.18. System Testing
The SI3232 includes a complete suite of test tools that provide the user with the ability to test the functionality of the line card as well as detect fault conditions present on the TIP/RING pair. Using the included loopback test mode along with the signal generation and measurement tools, the user can typically eliminate the need for per-line test relays as well as centralized test equipment.
4.18.1. Loopback Test Mode
Codec Loopback
TIP/ RING
ZA IBUF Gm
+ Mute ARX
From off-chip ADC
The codec loopback encompasses almost entirely the electronics of both the transmit and receive paths. The analog signal at the output of the system receive path DAC is fed back to the input of the transmit path by way of a feedback path. (See Figure 37.) The codec loopback mode is enabled by setting the DLM bit in the LBCON register. The impedance synthesis is disabled in this mode.
Figure 37. Digital Loopback Mode
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Table 32. Summary of Signal Generation and Measurement Tools
Function Range Signal Generation Tools Accuracy/ Resolution Comments
DC Current Generation DC Voltage Generation Ringing Signal Generation
18 to 45 mA 0 to 63.3 V 4 to 15 V 16 to 100 Hz
Measurement Tools
0.875 mA 1.005 V 5% 1%
8-Bit DC/Low Frequency Monitor A/D Converter
High Range: 0 to 160.173 V 0 to 101.09 mA Low Range: 0 to 64.07V 0 to 50.54 mA
628 mV 396.4 A 251 mV 198.2 A
800 Hz update rate ACrms, ACPK, and dc postprocessing blocks
AC Low-pass Filter
4.18.3. Signal Generation Tools
3 to 400 Hz resolution. ACrms, ACPK and dc filter blocks. Several postprocessing filter blocks are provided to allow the measured parameters to be processed according to the desired result. SLIC diagnostics filter Several post-processing filter blocks are provided for monitoring PEAK, dc, and ac characteristics of the Monitor A/D converter outputs as well as values derived from these outputs. Setting the SDIAG bit in the DIAG register enables the filters. There are separate filters for each channel, and their control is independent. The following parameters can be selected as inputs to the diagnostic block by setting the SDIAG_IN bits in the DIAG register to values 0-5 corresponding to the order below: VTIP = voltage on the TIP lead VRI NG = voltage on the RING lead VLOOP = VTIP-VRING = metallic (loop) voltage VLONG = (VTIP+VRING)/2 = longitudinal voltage ILOOP = ITIP-IRING = metallic (loop) current ILONG = (ITIP+IRING)/2 = longitudinal current The SLIC diagnostic capability consists of a peak detect block and two filter blocks, one for dc and one for ac. The topology is illustrated in Figure 38.
TIP/RING dc signal generation. The SI3232 linefeed D/A converter can program a constant current linefeed from 18-45 mA in 0.87 mA steps with a 10% total accuracy. In addition, the opencircuit TIP/RING voltage can be programmed from 0 to 63 V in 1 V steps. The linefeed circuitry also has the ability to generate a controlled polarity reversal. Diagnostics mode ringing generation. The SI3232 can generate an internal low-level ringing signal to test for the presence of REN without causing the terminal equipment to ring audibly. This ringing signal can be either balance or unbalanced depending on the state of the RINGUNB bit of the RINGCON register and the amplitude of the battery supplies present. 4.18.4. Measurement Tools 8-Bit monitor A/D converter. This 8-bit A/D converter monitors all dc and low-frequency voltage and current data from TIP to ground and RING to ground. Two additional values, TIP-RING and TIP+RING, are calculated and stored in on-chip registers for analyzing metallic and longitudinal effects. The A/D operates at an 800 Hz update rate to allow measurement bandwidth from dc to 400 Hz. A dual-range capability allows high-voltage/highcurrent measurement in the high range but can also measure lower voltages and currents with a tighter
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PEAK DETECT VTIP VRING VLOOP VLONG ILOOP ILONG FULL WAVE RECTIFIER The peak detect filter block will report the magnitude of the largest positive or negative value without sign. The dc filter block consists of a single pole IIR low-pass filter with a coefficient held in the DIAGDCCO indirect register. The filter output can be read from the DIAG_DC indirect register. The ac filter block consists of a full-wave rectifier followed by a single-pole IIR lowpass filter with a coefficient held in the DIAGACCO indirect register. The peak value can be read from the DIAGPK indirect register. The peak value is automatically cleared, and the filters are flushed on the 0-1 transition of the SDIAG bit as well as any time the input source is changed. The user can always write 0 to the DIAGPK register to get peak information for a specific time interval.
4.18.5. Diagnostics Capabilities Foreign voltages test. The SI3232 can detect the presence of foreign voltages according to GR-909 requirements of ac voltages > 10 V and dc voltages > 6 V from T-G or R-G. This test should only be performed once it has been determined that a hazardous voltage is not present on the line. Resistive faults test. Resistive fault conditions can be measured from T-G, R-G, or T-R for dc resistance per GR-909 specifications. If the dc resistance is < 150 k, it is considered a resistive fault. This test can be performed by programming the SI3232 to generate a constant open-circuit voltage and measuring the resulting current. The resistance can then be calculated in the system DSP. Receiver off-hook test. This test can use a similar procedure as outlined in the Resistive Faults test above but is measured only across T-R. In addition, two measurements must be performed at different open-circuit voltages in order to verify the resistive
DIAGACCO DIAGDCCO
SDIAG_PK
LPF
SDIAG_DC
LPF
SDIAG_AC
Figure 38. SLIC Diagnostic Filter Structure
linearity. If the calculated resistance has more than 15% nonlinearity between the two calculated points and the voltage/current origin, it is determined to be a resistive fault. Ringers (REN) test. This test verifies the presence of REN at the end of the TIP/RING pair per GR-909 specifications. It can be implemented by generating a 20 Hz ringing signal between 7 Vrms and 17 Vrms and measuring the 20 Hz ac current using the 8-bit monitor ADC. The resistance (REN) can then be calculated using the system DSP. The acceptable REN range is > 0.175 REN (<40 k) or < 5 REN (> 1400 ). A returned value of <1400 is determined to be a resistive fault from T-R, and a returned value > 40 k is determined to be a loop with no handset attached. AC line impedance measurement. This test can determine the loop length across T-R. It can be implemented by sending out multiple discrete tones from the system DSP/codec, one at a time, and measuring the returned amplitude, with the system hybrid balance filter disabled. By calculating the voltage difference between the initial amplitude and the received amplitude and dividing the result by the audio current, the line impedance can then be calculated in the system processor. Line capacitance measurement. This test can be implemented in the same manner as the ac line impedance measurement test above, but the frequency band of interest is between 1 kHz and 3.4 kHz. Knowing the synthesized 2-wire impedance of the SI3232, the roll-off effect can be used to calculate the ac line capacitance. An external codec is required for this test.
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Ringing voltage verification. This test verifies that the desired ringing signal has been correctly applied to the TIP/RING pair and can be measured in the 8bit monitor ADC, which senses low-frequency signals directly across T-R. Power induction measurement. This test can detect the presence of a power supply coupled onto the TIP/RING pair. It can be implemented by measuring the energy content at 50/60 Hz (normal induction) or at 100/120 Hz (rectified power induction). This is achieved by measuring the line voltage using a low-pass filter in the system DSP on the 8-bit monitor ADC while making certain there is no ringing signal present on the line.
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5. 8-Bit Control Register Summary1,2
Any register not listed here is reserved and must not be written. Shaded registers are read only. All registers are assigned a default value during initialization and following a system reset. Only registers 0, 2, 3, and 14 are available until a PLL lock is established or during a clock failure.
(Ordered alphabetically by mnemonic.)
Reg Addr3 Mnemonic Description Bit 7 Bit 6 Bit 5 Audio 21 AUDGAIN Audio Gain Control CMTXSEL ATXMUTE Calibration 11 12 CALR1 CALR2 Calibration Register 1 Calibration Register 2 CAL CALOFFR CALLKGR CALOFFT CALLKGT CALOFFRN CALMADC CALOFFTN CALDACO CALDIFG CALADCO CALCMG CALCMBAL Init Init R/W R/W 0x3F 0x3F ATX ARXMUTE ARX[1:0] Init R/W 0x00 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W Def. Hex
Diagnostic Tools 13 DIAG Diagnostics Tool Enable IQ2HR IQ1HR TSTRING Chip ID 0 ID Chip ID PARTNUM[2:0]4 Loop Current Limit 10 ILIM Loop Current Limit Interrupts 14 15 16 17 18 19 20 IRQ0 IRQ1 IRQ2 IRQ3 IRQEN1 IRQEN2 IRQEN3 Interrupt Status 0 Interrupt Status 1 Interrupt Status 2 Interrupt Status 3 Interrupt Enable 1 Interrupt Enable 2 Interrupt Enable 3 CMBALE CMBALS PULSTAE PULSTIE CLKIRQ4,6 PULSTAS IRQ3B4,6 PULSTIS IRQ2B4,6 RINGTAS RAMIRS PQ6S RINGTAE RAMIRE PQ6E IRQ1B4,6 RINGTIS DTMFS PQ5S RINGTIE DTMFE PQ5E VOCTRKE PQ4E LONGE PQ3E LOOPE PQ2E RTRIPE PQ1E VOCTRKS PQ4S LONGS PQ3S LOOPS PQ2S RTRIPS PQ1S IRQ3A4,6 IRQ2A4,6 IRQ1A4,6 Oper Oper Oper Oper Init Init Init R R/W R/W R/W R/W R/W R/W 0x00 0x00 0x00 0x00 0x00 0x00 0x00 ILIM[4:0] Init R/W 0x05 REV[3:0]4 Init R 0x-- TXFILT SDIAG SDIAGIN[2:0] Diag R/W
Loopback Enable 22 LBCON Loopback Enable DLM Linefeed Control 9 6 LCRRTP LINEFEED Loop Closure/Ring Trip/ Ground Key Detection Linefeed CMH4 LFS[2:0]4 SPI 2 3 MSTREN MSTRSTAT Master Initialization Enable Master Initialization Status PLLFLT PLLFAULT FSFLT FSFAULT PCFLT PCFAULT SRCLR4 PLOCK4 FSDET4 FSVAL4 PCVAL4 Init Init R/W R/W 0x00 0x00 SPEED4 VOCTST4 LONGHI4 RTP4 LF[2:0] LCR4 Oper Oper R R/W 0x40 0x00 Diag R/W 0x00
Pulse Metering 28 30 PMCON PMTAHI Pulse Metering Control Pulse Metering Oscillator Active Timer-- High Byte Pulse Metering Oscillator Active Timer-- Low Byte ENSYNC4,7 TAEN17 TIEN17 PULSE17 Oper Init R/W R/W 0x00 0x00
PULSETA[15:8]7
29
PMTALO
PULSETA[7:0]7
Init
R/W
0x00
Notes: 1. 2. 3. 4. 5. 6. 7.
Any register not listed is reserved and must not be written. Default hex value is loaded to register following any RESET. Only registers ID, MSTREN, MSTRSTAT, and IRQ0 are valid while the PLL is not locked (MSTRSTAT[PLOCK]). Reserved bit values are indeterminate. Register address is in decimal. Read only. Protected bits. Per-channel bit(s). Si3220 only.
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Reg Addr3 32 Mnemonic PMTIHI Description Pulse Metering Oscillator Inactive Timer-- High Byte Pulse Metering Oscillator Inactive Timer-- Low Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type Init R/W R/W Def. Hex 0x00 PULSETI[15:8]7
31
PMTILO
PULSETI[7:0]7
Init
R/W
0x00
Polarity Reversal 7 POLREV Polarity Reversal Settings RAM Access 103 102 101 4 RAMADDR RAMDATHI RAMDATLO RAMSTAT RAM Address RAM Data-- High Byte RAM Data-- Low Byte RAM Address Status Soft Reset 1 RESET Soft Reset Ringing 23 25 24 27 26 RINGCON RINGTAHI RINGTALO RINGTIHI RINGTILO Ringing Configuration Ringing Oscillator Active Timer--High Byte Ringing Oscillator Active Timer--Low Byte Ringing Oscillator Inactive Timer--High Byte Ringing Oscillator Inactive Timer--Low Byte ENSYNC4 RDACEN4 RINGUNB TAEN TIEN RINGEN4 UNBPOLR TRAP Init Init Init Init Init R/W R/W R/W R/W R/W 0x00 0x00 0x00 0x00 0x00 RESETB RESETA Init R/W 0x00 RAMADDR[7:0] RAMDAT[15:8] RAMDAT[7:0] RAMSTAT4 Oper Oper Oper Init R/W R/W R/W R 0x00 0x00 0x00 0x00 POLREV4 VOCZERO PREN RAMP Init R/W
RINGTA[15:8] RINGTA[7:0] RINGTI[15:8] RINGTI[7:0] Relay Configuration
5
RLYCON
Relay Driver and Battery Switching Configuration
BSEL5
RRAIL
RDOE
GPO
Diag
R/W
0x00
SLIC Bias Control 8 SBIAS SLIC Bias Control STDBY5 SQLCH5 CAPB5 BIASEN5 OBIAS[1:0]5 ABIAS[1:0]5 Init R/W 0xE0
Si3200 Thermometer 72 THERM Si3200 Thermometer STAT4 SEL5 Impedance Synthesis Coefficients 33 34 Notes: 1. 2. 3. 4. 5. 6. 7. ZRS ZZ Impedance Synthesis Analog Real Coeff Impedance Synthesis Analog Complex Coeff ZSDIS6 ZSOHT6 ZP[1:0]6 RS[3:0]6 ZZ[1:0]6 Init Init R/W R/W 0x00 0x00 Oper R/W 0x45
Any register not listed is reserved and must not be written. Default hex value is loaded to register following any RESET. Only registers ID, MSTREN, MSTRSTAT, and IRQ0 are valid while the PLL is not locked (MSTRSTAT[PLOCK]). Reserved bit values are indeterminate. Register address is in decimal. Read only. Protected bits. Per-channel bit(s). Si3220 only.
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6. 8-Bit Control Descriptions
AUDGAIN: Audio Gain Control (Register Address 21)
(Register type: Initialization)
D7 Name Type
D6
D5
D4
D3
D2
D1
D0
CMTXSEL R/W
ATXMUTE R/W
ATX R/W
ARXMUTE R/W
ARX[1:0] R/W
Reset settings = 0x00
Bit Name Function Transmit Path Common Mode Select. Selects common mode reference for transmit audio signal. 0 = VTXP/N pins will be referred to internal 1.5 V VCM level. 1 = VTXP/N pins will be referred to external common-mode level presented at the VCM pin. Analog Transmit Path Mute. 0 = Transmit signal passed. 1 = Transmit signal muted.
7
CMTXSEL
6
ATXMUTE
5 4
Reserved ATX
Read returns zero.
Analog Transmit Path Attenuation Stage. Selects analog transmit path attenuation. See "4.14. Audio Path Processing" on page 48. 0 = No attenuation. 1 = -3 dB attenuation.
3 2
Reserved ARXMUTE
Read returns zero.
Analog Receive Path Mute. 0 = Receive signal passed. 1 = Receive signal muted. Analog Receive Path Attenuation Stage. Selects analog receive path attenuation. See "4.14. Audio Path Processing" . 00 = No attenuation. 01 = -3 dB attenuation. 10 = -6 dB attenuation. 11 = Reserved. Do not use.
1:0
ARX[1:0]
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CALR1: Calibration 1 (Register Address 11)
(Register type: Initialization)
Bit Name Type
D7
D6
D5
D4
D3
D2
D1
D0
CAL R/W
CALOFFR CALOFFT CALOFFRN CALOFFTN CALDIFG R/W R/W R/W R/W R/W
CALCMG R/W
Reset settings = 0x3F
Bit Name Function Calibration Control/Status Bit. Begins system calibration routine. 0 = Normal operation or calibration complete. 1 = Calibration in progress.
7
CAL
6 5
Reserved CALOFFR
Read returns zero.
RING Offset Calibration. 0 = Normal operation or calibration complete. 1 = Calibration enabled or in progress. TIP Offset Calibration. 0 = Normal operation or calibration complete. 1 = Calibration enabled or in progress. IRINGN Offset Calibration. 0 = Normal operation or calibration complete. 1 = Calibration enabled or in progress. ITIPN Offset Calibration. 0 = Normal operation or calibration complete. 1 = Calibration enabled or in progress. Differential DAC Gain Calibration. 0 = Normal operation or calibration complete. 1 = Calibration enabled or in progress. Common Mode DAC Gain Calibration. 0 = Normal operation or calibration complete. 1 = Calibration enabled or in progress.
4
CALOFFT
3
CALOFFRN
2
CALOFFTN
1
CALDIFG
0
CALCMG
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CALR2: Calibration 2 (Register Address 12)
(Register type: Initialization)
Bit Name Type
D7
D6
D5
D4
D3
D2
D1
D0
CALLKGR R/W
CALLKGT R/W
CALMADC CALDACO CALADCO CALCMBAL R/W R/W R/W R/W
Reset settings = 0x3F
Bit Name Function
7:6 5
Reserved CALLKGR
Read returns zero.
RING Leakage Calibration. 0 = Normal operation or calibration complete. 1 = Calibration enabled or in progress. TIP Leakage Calibration. 0 = Normal operation or calibration complete. 1 = Calibration enabled or in progress. Monitor ADC Calibration. 0 = Normal operation or calibration complete. 1 = Calibration enabled or in progress. DAC Offset Calibration. Calibrates the audio DAC offset. 0 = Normal operation or calibration complete. 1 = Calibration enabled or in progress. ADC Offset Calibration. Calibrates the audio ADC offset. 0 = Normal operation or calibration complete. 1 = Calibration enabled or in progress. Common Mode Balance Calibration. Calibrates the ac longitudinal balance. 0 = Normal operation or calibration complete. 1 = Calibration enabled or in progress.
4
CALLKGT
3
CALMADC
2
CALDACO
1
CALADCO
0
CALCMBAL
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DIAG: Diagnostic Tools (Register Address 13)
(Register type: Diagnostics)
Bit Name Type
D7
D6
D5
D4
D3
D2
D1
D0
IQ2HR R/W
IQ1HR R/W
TSTRING R/W
TXFILT R/W
SDIAG R/W
SDIAGIN[2:0] R/W
Reset settings = 0x00
Bit Name Function Monitor ADC IQ2 High-Resolution Enable. Sets MADC to high-resolution range for IQ2 conversion. 0 = MADC not set to high resolution. 1 = MADC set to high resolution. Monitor ADC IQ1 High-Resolution Enable. Sets MADC to high-resolution range for IQ1 conversion. 0 = MADC not set to high resolution. 1 = MADC set to high resolution. Test Ringing Generator Enable. Enables the capability of generating a low-level ringing signal for diagnostic purposes. 0 = Test-ringing generator disabled. 1 = Test-ringing generator enabled. Transmit Path Audio Diagnostics Filter Enable. Enables the transmit path diagnostics filters. 0 = Transmit audio path diagnostics filters disabled. 1 = Transmit audio path diagnostics filters enabled. SLIC Diagnostics Filter Enable. Enables the SLIC path diagnostics filters. 0 = SLIC diagnostics filters disabled. 1 = SLIC diagnostics filters enabled. SLIC Diagnostics Filter Input. Selects the input to the SLIC diagnostics filter for dc and low-frequency line parameters. 000 = TIP voltage. 001 = RING voltage. 010 = Loop voltage, VTIP - VRING. 011 = Longitudinal voltage, (VTIP + VRING)/2. 100 = Loop (metallic) current. 101 = Longitudinal current.
7
IQ2HR
6
IQ1HR
5
TSTRING
4
TXFILT
3
SDIAG
2:0
SDIAGIN[2:0]
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SI3232
ID: Chip Identification (Register Address 0)
(Register type: Initialization/single value instance for both channels)
Bit Name Type
D7
D6
D5
D4
D3
D2
D1
D0
PARTNUM[2:0] R
REV[3:0] R
Reset settings = 0xxx
Bit Name Function
7 6:4
Reserved
Read returns zero.
PARTNUM[2:0] Part Number Identification. 000-010 = Reserved 011 = SI3232 100-111 = Reserved REV[3:0]
Revision Number Identification. 0001 = Revision A 0010 = Revision B 0011 = Revision C 0100 = Revision D 0101 = Revision E 0110 = Revision F 0111 = Revision G
3:0
ILIM: Loop Current Limit (Register Address 10)
(Register type: Initialization)
Bit Name Type
D7
D6
D5
D4
D3
D2
D1
D0
ILIM[4:0] R/W
Reset settings = 0x05
Bit Name Function
7:5 4:0
Reserved ILIM[4:0]
Read returns zero.
Loop Current Limit. The value written to this register sets the constant loop current. The value may be set between 18 mA (0x00) and 45 mA (0x20) in 0.875 mA steps.
Preliminary Rev. 0.96
67
SI3232
IRQ0: Interrupt Status 0 (Register Address 14)
(Register type: Operational/single value instance for both channels)
Bit Name Type
D7
D6
D5
D4
D3
D2
D1
D0
CLKIRQ R
IRQ3B R
IRQ2B R
IRQ1B R
IRQ3A R
IRQ2A R
IRQ1A R
Reset settings = 0x00 Read this interrupt to indicate which interrupt status byte, from which channel, has a pending interrupt.
Bit Name Function Clock Failure Interrupt Pending. 0 = No interrupt pending. 1 = Clock failure interrupt pending. Clock failure status indicated in MSTRSTAT register, bits 7:5. Interrupt Pending. 0 = No interrupt pending. 1 = Interrupt pending in interrupt status byte 3 (IRQ3) for channel B. Interrupt Pending. 0 = No interrupt pending. 1 = Interrupt pending in interrupt status byte 2 (IRQ2) for channel B. Interrupt Pending. 0 = No interrupt pending. 1 = Interrupt pending in interrupt status byte 1 (IRQ1) for channel B.
7
CLKIRQ
6
IRQ3B
5
IRQ2B
4
IRQ1B
3 2
Reserved IRQ3A
Read returns zero.
Interrupt Pending. 0 = No interrupt pending. 1 = Interrupt pending in interrupt status byte 3 (IRQ3) for channel A. Interrupt Pending. 0 = No interrupt pending. 1 = Interrupt pending in interrupt status byte 2 (IRQ2) for channel A. Interrupt Pending. 0 = No interrupt pending. 1 = Interrupt pending in interrupt status byte 1 (IRQ1) for channel A.
1
IRQ2A
0
IRQ1A
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Preliminary Rev. 0.96
SI3232
IRQ1: Interrupt Status 1 (Register Address 15)
(Register type: Operational/bits writable in GCI mode only)
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name PULSTAS PULSTIS RINGTAS Type
RINGTIS R/W
R/W
R/W
R/W
Reset settings = 0x00
Bit Name Function Pulse Metering Active Timer Interrupt Pending. 0 = No interrupt pending. 1 = Interrupt pending. Pulse Metering Inactive Timer Interrupt Pending. 0 = No interrupt pending. 1 = Interrupt pending. Ringing Active Timer Interrupt Pending. 0 = No interrupt pending. 1 = Interrupt pending. Ringing Inactive Timer Interrupt Pending. 0 = No interrupt pending. 1 = Interrupt pending.
7
PULSTAS
6
PULSTIS
5
RINGTAS
4
RINGTIS
3:0
Reserved
Read returns zero.
Preliminary Rev. 0.96
69
SI3232
IRQ2: Interrupt Status 2 (Register Address 16)
(Register type: Operational/bits writable in GCI mode only)
Bit Name Type
D7
D6
D5
D4
D3
D2
D1
D0
RAMIRS R/W
DTMFS R/W
VOCTRKS R/W
LONGS R/W
LOOPS R/W
RTRIPS R/W
Reset settings = 0x00
Bit Name Function
7:6 5
Reserved RAMIRS
Read returns zero.
RAM Access Interrupt Pending. 0 = No interrupt pending. 1 = Interrupt pending. DTMF Tone Detect Interrupt Pending. 0 = No interrupt pending. 1 = Interrupt pending. VOC Tracking Interrupt Pending. 0 = No interrupt pending. 1 = Interrupt pending. Ground Key Interrupt Pending. 0 = No interrupt pending. 1 = Interrupt pending. Loop Closure Interrupt Pending. 0 = No interrupt pending. 1 = Interrupt pending. Ring Trip Interrupt Pending. 0 = No interrupt pending. 1 = Interrupt pending.
4
DTMFS
3
VOCTRKS
2
LONGS
1
LOOPS
0
RTRIPS
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Preliminary Rev. 0.96
SI3232
IRQ3: Interrupt Status 3 (Register Address 17)
(Register type: Operational/bits writable in GCI mode only)
Bit Name Type
D7
D6
D5
D4
D3
D2
D1
D0
CMBALS R/W
PQ6S R/W
PQ5S R/W
PQ4S R/W
PQ3S R/W
PQ2S R/W
PQ1S R/W
Reset settings = 0x00
Bit Name Function Common Mode Balance Interrupt Pending. 0 = No interrupt pending. 1 = Interrupt pending.
7
CMBALS
6 5
Reserved PQ6S
Read returns zero.
Power Alarm Q6 Interrupt Pending. 0 = No interrupt pending. 1 = Interrupt pending. Power Alarm Q5 Interrupt Pending. 0 = No interrupt pending. 1 = Interrupt pending. Power Alarm Q4 Interrupt Pending. 0 = No interrupt pending. 1 = Interrupt pending. Power Alarm Q3 Interrupt Pending. 0 = No interrupt pending. 1 = Interrupt pending. Power Alarm Q2 Interrupt Pending. 0 = No interrupt pending. 1 = Interrupt pending. Power Alarm Q1 Interrupt Pending. 0 = No interrupt pending. 1 = Interrupt pending.
4
PQ5S
3
PQ4S
2
PQ3S
1
PQ2S
0
PQ1S
Preliminary Rev. 0.96
71
SI3232
IRQEN1: Interrupt Enable 1 (Register Address 18)
(Register type: Initialization)
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name PULSTAE PULSTIE RINGTAE Type
RINGTIE R/W
R/W
R/W
R/W
Reset settings = 0x00
Bit Name Function Pulse Metering Active Timer Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. Pulse Metering Inactive Timer Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. Ringing Active Timer Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. Ringing Inactive Timer Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled.
7
PULSTAE
6
PULSTIE
5
RINGTAE
4
RINGTIE
3:0
Reserved
Read returns zero.
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Preliminary Rev. 0.96
SI3232
IRQEN2: Interrupt Enable 2 (Register Address 19)
(Register type: Initialization)
Bit Name Type
D7
D6
D5
D4
D3
D2
D1
D0
RAMIRE R/W
DTMFE R/W
VOCTRKE R/W
LONGE R/W
LOOPE R/W
RTRIPE R/W
Reset settings = 0x00
Bit Name Function
7:6 5
Reserved RAMIRE
Read returns zero.
RAM Access Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. DTMF Tone Detect Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. VOC Tracking Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. Ground Key Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. Loop Closure Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. Ring Trip Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled.
4
DTMFE
3
VOCTRKE
2
LONGE
1
LOOPE
0
RTRIPE
Preliminary Rev. 0.96
73
SI3232
IRQEN3: Interrupt Enable 3 (Register Address 20)
(Register type: Initialization)
Bit Name Type
D7
D6
D5
D4
D3
D2
D1
D0
CMBALE R/W
PQ6E R/W
PQ5E R/W
PQ4E R/W
PQ3E R/W
PQ2E R/W
PQ1E R/W
Reset settings = 0x00
Bit Name Function Common Mode Balance Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled.
7
CMBALE
6 5
Reserved PQ6E
Read returns zero.
Power Alarm Q6 Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. Power Alarm Q5 Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. Power Alarm Q4 Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. Power Alarm Q3 Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. Power Alarm Q2 Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. Power Alarm Q1 Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled.
4
PQ5E
3
PQ4E
2
PQ3E
1
PQ2E
0
PQ1E
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Preliminary Rev. 0.96
SI3232
LBCON: Loopback Enable (Register Address 22)
(Register type: Diagnostic)
Bit Name Type Bit 7
D7
D6
D5
D4
D3
D2
D1
D0
DLM R/W
Name DLM Function Codec Loopback Mode Enable. 0 = Codec loopback mode disabled. 1 = Codec loopback mode enabled. Read returns zero.
Reset settings = 0x00
6:0
Reserved
LCRRTP: Loop Closure/Ring Trip/Ground Key Detection (Register Address 9)
(Register type: Operational)
Bit Name
D7
D6
D5
D4
D3
D2
D1
D0
CMH R
SPEED R
VOCTST R
LONGHI R
RTP R
LCR R
Type Reset settings = 0x40 Bit 7:6 5 Name Reserved CMH
Function
4
SPEED
3
VOCTST
Read returns zero. Common Mode High Threshold. Indicates that common-mode threshold has been exceeded. 0 = Common-mode threshold not exceeded. 1 = Common-mode threshold exceeded. Speedup Mode Enable. 0 = Speedup disabled. 1 = Automatic speedup. VOC Tracking Status. Indicates that battery voltage has dropped and VOC tracking is enabled. 0 = VOC tracking threshold not exceeded, VTR on-hook = VOC. 1 = VOC tracking threshold exceeded, VTR on-hook = VOCtrack. Ground Key Detect Flag. 0 = Ground key event has not been detected. 1 = Ground key event has been detected. Ring Trip Detect Flag. 0 = Ring trip event has not been detected. 1 = Ring trip event has been detected. Loop Closure Detect Flag. 0 = Loop closure event has not been detected. 1 = Loop closure event has been detected.
2
LONGHI
1
RTP
0
LCR
Note: Detect bits are not sticky bits. Refer to interrupt status for interrupt bit history indication.
Preliminary Rev. 0.96
75
SI3232
LINEFEED: Linefeed Control (Register Address 6)
(Register type: Operational)
Bit Name Type
D7
D6
D5
D4
D3
D2
D1
D0
LFS[2:0] R
LF[2:0] R/W
Reset settings = 0x00
Bit Name Function
7 6:4
Reserved LFS[2:0]
Read returns zero.
Linefeed Shadow. This register reflects the actual realtime linefeed status. Automatic operations may cause actual linefeed state transitions regardless of the Linefeed register settings (e.g., when the Linefeed register is in the ringing state, the Linefeed Shadow register will reflect the ringing state during ringing bursts and the OHT state during silent periods between ringing bursts). 000 = Open 001 = Forward Active 010 = Forward On-hook Transmission (OHT) 011 = TIP Open 100 = Ringing 101 = Reverse Active 110 = Reverse On-hook Transmission 111 = RING Open
3 2:0
Reserved LF[2:0]
Read returns zero.
Linefeed. Writing to this register sets the linefeed state. 000 = Open 001 = Forward Active 010 = Forward On-hook Transmission (OHT) 011 = TIP Open 100 = Ringing 101 = Reverse Active 110 = Reverse On-hook Transmission 111 = RING Open
76
Preliminary Rev. 0.96
SI3232
MSTREN: Master Initialization Enable (Register Address 2)
(Register type: Initialization/single value instance for both channels)
Bit Name Type
D7
D6
D5
D4
D3
D2
D1
D0
PLLFLT R/W
FSFLT R/W
PCFLT R/W
Reset settings = 0x00
Bit Name Function PLL Lock Fault Enable. 0 = PLLFAULT interrupt bit is enabled. 1 = PLLFAULT interrupt bit is disabled. FSYNC Clock Fault Enable. 0 = FSYNC interrupt bit is enabled. 1 = FSYNC interrupt bit is disabled. PCM Clock Fault Enable. 0 = PCM interrupt bit is enabled. 1 = PCM interrupt bit is disabled.
7
PLLFLT
6
FSFLT
5
PCFLT
4:0
Reserved
Read returns zero.
Preliminary Rev. 0.96
77
SI3232
MSTRSTAT: Master Initialization Status (Register Address 3)
(Register type: Initialization/single value instance for both channels)
Bit Type
D7
D6
D5
D4
D3
D2
D1
D0
Name PLLFAULT FSFAULT PCFAULT
SRCLR R
PLOCK R
FSDET R
FSVAL R
PCVAL R
R/W
R/W
R/W
Reset settings = 0x00
Bit 7 Name PLLFAULT Function PLL Lock Fault Status. This bit is set when the PLOCK bit transitions low, indicating loss of PLL lock. Writing 1 to this bit clears the status. 0 = PLL lock is valid. 1 = PLL has lost lock. FSYNC Clock Fault Status. This bit is set when the FSVAL and FSDET bits transition low, indicating loss of valid FSYNC signal or invalid FSYNC-to-PCLK ratio. Writing 1 to this bit clears the status. 0 = Correct FSYNC to PCLK ration present. 1 = FSYNC to PCLK ratio lost. PCM Clock Fault Status. This bit will be set when the PCVAL bit transitions low. Writing 1 to this bit clears the status. 0 = Valid PCLK signal present. 1 = No valid PCLK signal present. SRAM Clear Status Detect. 0 = SRAM clear operation not initiated or in progress. 1 = SRAM clear operation has completed. PLL Lock Detect. Indicates the internal PLL is locked relative to FSYNC. 0 = PLL has lost lock relative to FSYNC. 1 = PLL locked relative to FSYNC. FSYNC to PCLK Ratio Detect. Indicates a valid FSYNC to PCLK ratio has been detected. 0 = Invalid FSYNC to PCLK ratio detected. 1 = Correct FSYNC to PCLK ratio present. FSYNC Clock Valid. Indicates that a minimum valid FSYNC signal is present. 0 = FSYNC signal is not valid. 1 = FSYNC signal is present. PCM Clock Valid. Indicates that a minimum valid PCLK signal is present. 0 = PCLK signal is 128 kHz. 1 = PCLK signal is 128 kHz.
6
FSFAULT
5
PCFAULT
4
SRCLR
3
PLOCK
2
FSDET
1
FSVAL
0
PCVAL
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Preliminary Rev. 0.96
SI3232
PMCON: Pulse Metering Control (Register Address 28)
(Register type: Operational)
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name ENSYNC Type
TAEN1 R/W
TIEN1 R/W
PULSE1 R/W
R
Reset settings = 0x00
Bit Name Function Pulse Metering Waveform Present Flag. Indicates a pulse-metering waveform is present. 0 = No pulse metering waveform present. 1 = Pulse metering waveform present.
7
ENSYNC
6:5 4
Reserved TAEN1
Read returns zero.
Pulse Metering Active Timer Enable. 0 = Timer disabled. 1 = Timer enabled. Pulse Metering Inactive Timer Enable. 0 = Timer disabled. 1 = Timer enabled. Pulse Metering Enable. 0 = Pulse metering disabled. 1 = Pulse metering enabled.
3
TIEN1
2
PULSE1
1:0
Reserved
Read returns zero.
PMTAHI: Pulse Metering Oscillator Active Timer--High Byte (Register Address 30)
(Register type: Initialization)
Bit Name Type
D7
D6
D5
D4
D3
D2
D1
D0
PULSETA[15:8] R/W
Reset settings = 0x00
Bit Name Function
7:0
PULSETA[15:8] Pulse Metering Oscillator Active Timer. This register contains the upper 8 bits of the pulse metering oscillator active timer. Register 29 contains the lower 8 bits of this value.
Preliminary Rev. 0.96
79
SI3232
PMTALO: Pulse Metering Oscillator Active Timer--Low Byte (Register Address 29)
(Register type: Initialization)
Bit Name Type
D7
D6
D5
D4
D3
D2
D1
D0
PULSETA[7:0] R/W
Reset settings = 0x00
Bit Name Function Pulse Metering Oscillator Active Timer. This register contains the lower 8 bits of the pulse-metering oscillator active timer. Register 30 contains the upper 8 bits of this value. 1.25 s/LSB.
7:0
PULSETA[7:0]
PMTIHI: Pulse Metering Oscillator Inactive Timer--High Byte (Register Address 32)
(Register type: Initialization)
Bit Name Type
D7
D6
D5
D4
D3
D2
D1
D0
PULSETI[15:8] R/W
Reset settings = 0x00
Bit Name Function
7:0
PULSETI[15:8] Pulse Metering Oscillator Inactive Timer. This register contains the upper 8 bits of the pulse-metering oscillator inactive timer. Register 29 contains the lower 8 bits of this value.
PMTILO: Pulse Metering Oscillator Inactive Timer--Low Byte (Register Address 31)
(Register type: Initialization)
Bit Name Type
D7
D6
D5
D4
D3
D2
D1
D0
PULSETI[7:0] R/W
Reset settings = 0x00
Bit Name Function Pulse Metering Oscillator Inactive Timer. This register contains the lower 8 bits of the pulse-metering oscillator inactive timer. Register 30 contains the upper 8 bits of this value. 1.25 s/LSB.
7:0
PULSETI[7:0]
80
Preliminary Rev. 0.96
SI3232
POLREV: Polarity Reversal Settings (Register Address 7)
(Register type: Initialization)
Bit Name Type
D7
D6
D5
D4
D3
D2
D1
D0
POLREV R
VOCZERO R/W
PREN R/W
RAMP R/W
Reset settings = 0x00
Bit Name Function
7:4 3
Reserved POLREV
Read returns zero.
Polarity Reversal Status. 0 = Forward polarity. 1 = Reverse polarity. Wink Function Control. Enables a wink function by decrementing the open circuit voltage to zero. 0 = Maintain current VOC value. 1 = Decrement VOC voltage to 0 V. Smooth Polarity Reversal Enable. 0 = Disabled. 1 = Enabled. Smooth Polarity Reversal Ramp Rate. 0 = 1 V/1.25 ms ramp rate. 1 = 2 V/1.25 ms ramp rate.
2
VOCZERO
1
PREN
0
RAMP
RAMADDR: RAM Address (Register Address 103)
(Register type: Operational/single value instance for both channels)
Bit Name Type
D7
D6
D5
D4
D3
D2
D1
D0
RAMADDR[7:0] R/W
Reset settings = 0x00
Bit Name Function
7:0
RAMADDR[7:0] RAM Data--Low Byte. A write to RAMDAT followed by a write to RAMADDR places the contents of RAMDAT into a RAM location specified by the RAMADDR at the next memory update (WRITE operation). Writing RAMADDR loads the data stored in RAMADDR into RAMDAT only at the next memory update (READ operation).
Preliminary Rev. 0.96
81
SI3232
RAMDATHI: RAM Data--High Byte (Register Address 102)
(Register type: Operational/single value instance for both channels)
Bit Name Type
D7
D6
D5
D4
D3
D2
D1
D0
RAMDAT[15:8] R/W
Reset settings = 0x00
Bit Name Function
7:0
RAMDAT[15:8] RAM Data--High Byte. A write to RAMDAT followed by a write to RAMADDR places the contents of RAMDAT into a RAM location specified by the RAMADDR at the next memory update (WRITE operation). Writing RAMADDR loads the data stored in RAMADDR into RAMDAT only at the next memory update (READ operation).
RAMDATLO: RAM Data--Low Byte (Register Address 101)
(Register type: Operational/single value instance for both channels)
Bit Name Type
D7
D6
D5
D4
D3
D2
D1
D0
RAMDAT[7:0] R/W
Reset settings = 0x00
Bit Name Function
7:0
RAMDAT[15:8] RAM Data--Low Byte. A write to RAMDAT followed by a write to RAMADDR places the contents of RAMDAT into a RAM location specified by the RAMADDR at the next memory update (WRITE operation). Writing RAMADDR loads the data stored in RAMADDR only into RAMDAT at the next memory update (READ operation).
82
Preliminary Rev. 0.96
SI3232
RAMSTAT: RAM Address Status (Register Address 4)
(Register type: Operational)
Bit Name Type
D7
D6
D5
D4
D3
D2
D1
D0
RAMSTAT R
Reset settings = 0x00
Bit Name Function
7:1 0
Reserved RAMSTAT
Read returns zero.
RAM Address Status. 0 = RAM ready for access. 1 = RAM access pending internally (busy).
RESET: Soft Reset (Register Address 1)
(Register type: Initialization)
Bit Name Type
D7
D6
D5
D4
D3
D2
D1
D0
RESETB R/W
RESETA R/W
Reset settings = 0x00
Bit Name Function
7:2 1
Reserved RESETB
Read returns zero.
Soft Reset, Channel B. 0 = Normal operation. 1 = Initiate soft reset to Channel B. Soft Reset, Channel A. 0 = Normal operation. 1 = Initiate soft reset to Channel A.
0
RESETA
Note: Soft reset set to a single channel of a given device causes all register space to reset to default values for that channel. Soft reset set to both channels of a given device causes a hardware reset including PLL reinitialization and RAM clear.
Preliminary Rev. 0.96
83
SI3232
RINGCON: Ringing Configuration (Register Address 23)
(Register type: Initialization)
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name ENSYNC RDACEN RINGUNB Type
TAEN R/W
TIEN R/W
RINGEN R
UNBPOLR R/W
TRAP R/W
R
R
R/W
Reset settings = 0x00
Bit Name Function Ringing Waveform Present Flag. 0 = No ringing waveform present. 1 = Ringing waveform present. Ringing Waveform Sent to Differential DAC. 0 = Ringing waveform not sent to differential DAC. 1 = Ringing waveform set to differential DAC. Unbalanced Ringing Enable. Enables internal unbalanced ringing generation. 0 = Unbalanced ringing not enabled. 1 = Unbalanced ringing enabled. Ringing Active Timer Enable. 0 = Ringing active timer disabled. 1 = Ringing active timer enabled. Ringing Inactive Timer Enable. 0 = Ringing inactive timer disabled. 1 = Ringing inactive timer enabled. Ringing Oscillator Enable Monitor. This bit will toggle when the ringing oscillator is enabled and disabled. 0 = Ringing oscillator is disabled. 1 = Ringing oscillator is enabled. Reverse Polarity Unbalanced Ringing Select. The RINGOF RAM location must be modified from its normal ringing polarity setting. Refer to "4.7. Internal Unbalanced Ringing" for details. 0 = Normal polarity ringing. 1 = Reverse polarity ringing. Ringing Waveform Selection. 0 = Sinusoid waveform. 1 = Trapezoid waveform.
7
ENSYNC
6
RDACEN
5
RINGUNB
4
TAEN
3
TIEN
2
RINGEN
1
UNBPOLR
0
TRAP
84
Preliminary Rev. 0.96
SI3232
RINGTAHI: Ringing Oscillator Active Timer--High Byte (Register Address 25)
(Register type: Initialization)
Bit Name Type
D7
D6
D5
D4
D3
D2
D1
D0
RINGTA[15:8] R/W
Reset settings = 0x00
Bit Name Function Ringing Oscillator Active Timer. This register contains the upper 8 bits of the ringing oscillator active timer (the on-time of the ringing burst). Register 24 contains the upper 8 bits of this value.
7:0
RINGTA[15:8]
RINGTALO: Ringing Oscillator Active Timer--Low Byte (Register Address 24)
(Register type: Initialization)
Bit Name Type
D7
D6
D5
D4
D3
D2
D1
D0
RINGTA[7:0] R/W
Reset settings = 0x00
Bit Name Function Ringing Oscillator Active Timer. This register contains the lower 8 bits of the ringing oscillator active timer (the on-time of the ringing burst). Register 25 contains the upper 8 bits of this value. 1.25 s/LSB.
7:0
RINGTA[7:0]
RINGTIHI: Ringing Oscillator Inactive Timer--High Byte (Register Address 27)
(Register type: Initialization)
Bit Name Type
D7
D6
D5
D4
D3
D2
D1
D0
RINGTI[15:8] R/W
Reset settings = 0x00
Bit Name Function Ringing Oscillator Inactive Timer. This register contains the upper 8 bits of the ringing oscillator inactive timer (the silent period between ringing bursts). Register 26 contains the upper 8 bits of this value.
7:0
RINGTI[15:8]
Preliminary Rev. 0.96
85
SI3232
RINGTILO: Ringing Oscillator Inactive Timer--Low Byte (Register Address 26)
(Register type: Initialization)
Bit Name Type
D7
D6
D5
D4
D3
D2
D1
D0
RINGTI[7:0] R/W
Reset settings = 0x00
Bit Name Function Ringing Oscillator Inactive Timer. This register contains the lower 8 bits of the ringing oscillator inactive timer (the silent time between ringing bursts). Register 27 contains the upper 8 bits of this value. 1.25 s/ LSB.
7:0
RINGTI[7:0]
RLYCON: Relay Driver and Battery Switching Configuration (Register Address 5)
(Register type: Diagnostic)
Bit Name Type
D7
D6
D5
D4
D3
D2
D1
D0
BSEL R
RRAIL R/W
RDOE R/W
GPO R/W
Reset settings = 0xA3
Bit Name Function
7:6 5
Reserved BSEL
Read returns 10 binary.
Battery Select Indicator. 0 = BATSEL pin is output low. (Si3200 internal battery switch open). 1 = BATSEL pin is output high. (Si3200 internal battery switch closed). Additional Ringing Rail Present (Third Battery). 0 = Ringing rail not present. 1 = Ringing rail present. For Si3220, RRD/GPO toggles with LINEFEED ringing cadence. Relay Driver Output Enable. 0 = Disabled. 1 = Enabled. General Purpose Output. 0 = GPO output low. 1 = GPO output high.
4
RRAIL
3
RDOE
2
GPO
1:0
Reserved
Read returns zero.
86
Preliminary Rev. 0.96
SI3232
SBIAS: SLIC Bias Control (Register Address 8)
(Register type: Initialization/protected register bits)
Bit Name Type
D7
D6
D5
D4
D3
D2
D1
D0
STDBY R/W-P
SQLCH R/W-P
CAPB R/W-P
BIASEN R/W-P
OBIAS[1:0] R/W-P
ABIAS[1:0] R/W-P
Reset settings = 0xE0
Bit Name Function Low-power Standby Status. Writing to this bit causes temporary manual control of this bit until a subsequent on-hook or off-hook transition. 0 = low-power mode off (i.e. Active off-hook). 1 = low-power mode on (i.e. Active on-hook). Audio Squelch Control. Indicates squelch of audio during the setting time set by the SPEEDUP RAM coefficient. Writing to this bit causes temporary manual override until a speedup event occurs. 0 = Squelch off. 1 = Squelch on. Audio Filter Capacitor Bypass. Indicates filter capacitor pass during the setting time set by the SPEEDUP RAM coefficient. Writing to this bit causes temporary manual override until a speedup event occurs. 0 = Capacitors not bypassed. 1 = Capacitors bypassed. SLIC Bias Enable. Writing to this bit causes temporary manual control of SLIC bias until a subsequent onhook or off-hook state. 0 = SLIC bias off (i.e. Active on-hook). 1 = = SLIC bias on (i.e. Active off-hook). SLIC Bias Level, On-Hook Transmission State. DC bias current flowing in the SLIC circuit during on-hook transmission state. Increasing this value increases the ability of the SLIC to withstand longitudinal current artifacts. 00 = 4 mA per lead. 01 = 8 mA per lead. 10 = 12 mA per lead. 11 = 16 mA per lead. SLIC Bias Level, Active State. DC bias current flowing in the SLIC circuit during the active off-hook state. Increasing this value increases the ability of the SLIC to withstand longitudinal current artifacts. 00 = 4 mA per lead. 01 = 8 mA per lead. 10 = 12 mA per lead. 11 = 16 mA per lead.
7
STDBY
6
SQLCH
5
CAPB
4
BIASEN
3:2
OBIAS[1:0]
1:0
ABIAS[1:0]
Note: Bit type "P" = user-protected bits. Refer to the protected register bit section in the text of this application note.
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THERM: Si3200 Thermometer (Register Address 72)
(Register type: Diagnostic/single value instance for both channels)
Bit Name Type
D7
D6
D5
D4
D3
D2
D1
D0
STAT R
SEL R/W
Reset settings = 0x00
Bit Name Function Si3200 Thermometer Status. Reads whether the Si3200 has shut down due to an over-temperature event. 0 = Si3200 operating within normal operating temperature range. 1 = Si3200 has exceeded maximum operating temperature.
7
STAT
6
SEL
Si3200 Power Sensing Mode Select (Protected Register Bit). 0 = Transistor power sum used for power sensing (PSUM vs. threshold in PTH12) 1 = Si3200 therm diode used for power sensing. Read returns zero.
5:0
Reserved
ZRS: Impedance Synthesis--Analog Real Coefficient (Register Address 33)
(Register type: Initialization/single value instance for both channels)
Bit Name Type
D7
D6
D5
D4
D3
D2
D1
D0
RS[3:0] R/W
Reset settings = 0x00
Bit Name Function
7:4 3:0
Reserved RS[3:0]
Read returns zero.
Impedance Synthesis Analog Real Coefficient. Refer to coefficient generation program.
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ZZ: Impedance Synthesis--Analog Complex Coefficient (Register Address 34)
(Register type: Initialization/single value instance for both channels)
Bit Name Type
D7
D6
D5
D4
D3
D2
D1
D0
ZSDIS R/W
ZSOHT R/W
ZP[1:0] R/W
ZZ[1:0] R/W
Reset settings = 0x00
Bit Name Function Analog Impedance Synthesis Coefficient Disable. Enables/disables RS, ZSOHT, ZP, and ZZ coefficients. 0 = Analog ZSYNTH coefficients enabled. 1 = Analog ZSYNTH coefficients disabled. Analog Impedance Synthesis Complex Coefficients. Refer to coefficient generation program.
7
ZSDIS
6 5:4 3:2 1:0
ZSOHT ZP[1:0] Reserved ZZ[1:0]
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7. 16-Bit RAM Address Summary1
All internal 16-bit RAM addresses can be assigned unique values for each SLIC channel and are accessed in a similar manner as the 8-bit control registers except that the data are twice as long. In addition, one additional READ cycle is required during READ operations to accommodate the one-deep pipeline architecture. (See "4.16. SPI Control Interface" on page 50 for more details). All internal RAM addresses are assigned a default value of zero during initialization and following a system reset. Unless otherwise noted, all RAM addresses use a 2s complement, MSB first data format (ordered alphabetically by mnemonic).
RAM Addr Mnemonic Description Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type Ex. Hex Ex. Dec Unit
Battery Selection and VOC Tracking 31 BATHTH High Battery Switch Threshold Battery Tracking Filter Coeff Low Battery Switch Threshold RING Voltage Filter Coeff BATHTH[14:7]2 Init 0E54 18 V
34
BATLPF
BATLPF[15:3]
Init
0A08
10
32
BATLTH
BATLTH[14:7]2
Init
0D88
17
V
33
BSWLPF
BSWLPF[15:3] Speedup
Init
0A08
10
36
CMHITH
Speedup Threshold-- High Byte Speedup Threshold-- Low Byte
CMHITH[15:0]
Init
0001
1
V
35
CMLOTH
CMLOTH[15:0]
Init
07F5
10
V
SLIC Diagnostics Filter 53 DIAGAC SLIC Diags AC Detector Threshold SLIC Diags AC Filter Coeff SLIC Diags dc Output SLIC Diags dc Filter Coeff SLIC Diags Peak Detector DIAGAC[15:0] Diag V
54 51 52 55
DIAGACCO DIAGDC DIAGDCCO DIAGPK
DIAGACCO[15:3] DIAGDC[15:0] DIAGDCCO[15:3] DIAGPK[15:0]
Diag Diag Diag Diag
7FF8
127.3
Hz V
0A08
10
Hz V
Loop Currents 9 ILONG Longitudinal Current Sense Value Loop Current Sense Value Q5 Current Measurement Q3 Current Measurement Q2 Current Measurement Q6 Current Measurement Q4 Current Measurement Q1 Current Measurement ILONG[15:0]2 DIag mA
8 18 16 15 19 17 14
ILOOP IRING IRINGN IRINGP ITIP ITIPN ITIPP
ILOOP[15:0]2 IRING[15:0] IRINGN[15:0] IRINGP[15:0] ITIP[15:0] ITIPN[15:0] ITIPP[15:0] Loop Closure Detection
Diag Diag Diag Diag Diag Diag Diag
mA mA mA mA mA mA mA
24
LCRDBI
Loop Closure Detection Debounce Interval Loop Closure Filter Coeff
LCRDBI[15:0]2
Init
000C
15
ms
25 Notes: 1. 2.
LCRLPF
LCRLPF[15:3]
Init
0A10
10
RAM values are 2's complement unless otherwise noted. Any register not listed is reserved and must not be written. Only positive input values are valid for these RAM addresses.
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RAM Addr 26 Mnemonic LCRMASK Description Loop Closure Mask Interval Coeff LCR Mask During Polarity Reversal Off-Hook Detect Threshold On-Hook Detect Threshold Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type Init Ex. Hex 0040 Ex. Dec 80 Unit ms
LCRMASK[15:0]2
166
LCRMSKPR
LCRMSKPR[15:0]
Init
0040
80
ms
22 23
LCROFFHK LCRONHK
LCROFFHK[15:0]2 LCRONHK[15:0]2 Longitudinal Current Detection
Init Init
0C0C 0DE0
10 11
mA mA
29
LONGDBI
Ground Key Detection Debounce Interval Ground Key Detection Threshold Ground Key Removal Detection Threshold Ground Key Filter Coeff
LONGDBI[15:0]2
Init
ms
27
LONGHITH
LONGHITH[15:0]2
Init
08D4
7
mA
28
LONGLOTH
LONGLOTH[15:0]2
Init
0A17
8
mA
30
LONGLPF
LONGLPF[15:3] Power Filter Coefficients
Init
0A08
10
40
PLPF12
Q1/Q2 Thermal Low-pass Filter Coeff Q3/Q4 Thermal Low-pass Filter Coeff Q5/Q6 Thermal Low-pass Filter Coeff
PLPF12[15:3]
Init
0008
.3
s
41
PLPF34
PLPF34[15:3]
Init
0008
.3
s
42
PLPF56
PLPF56[15:3]
Init
0008
.3
s
Pulse Metering 68 70 PMAMPL PMAMPTH Pulse Metering Amplitude Pulse Metering AGC Amplitude Threshold Pulse Metering Frequency Pulse Metering Ramp Rate PMAMPL[15:0] PMAMPTH[15:0] Init Init 4000 00C8 65536 798 V V
67
PMFREQ
PMFREQ[15:3]
Init
0000
0
Hz
69
PMRAMP
PMRAMP[15:0] Power Calculations
Init
008A
550
s
44 45 46 47 48 49 50 37 38 39 43
PQ1DH PQ2DH PQ3DH PQ4DH PQ5DH PQ6DH PSUM PTH12 PTH34 PTH56 RB56
Q1 Calculated Power Q2 Calculated Power Q3 Calculated Power Q4 Calculated Power Q5 Calculated Power Q6 Calculated Power Total Calculated Power Q1/Q2 Power Threshold Q3/Q4 Power Threshold Q5/Q6 Power Threshold Q5/Q6 Base Resistor
PQ1DH[15:0] PQ2DH[15:0] PQ3DH[15:0] PQ4DH[15:0] PQ5DH[15:0] PQ6DH[15:0] PSUM[15:0] PTH12[15:0] PTH34[15:0] PTH56[15:0] RB56[15:0] Ringing
2 2 2
Diag Diag Diag Diag Diag Diag Diag Init Init Init Init 0007 003C 002A .22 17 1.28
W W W W W W W W W W
59 Notes: 1. 2.
RINGAMP
Ringing Amplitude
RINGAMP[15:0]
Init
00D5
47
Vrms
RAM values are 2's complement unless otherwise noted. Any register not listed is reserved and must not be written. Only positive input values are valid for these RAM addresses.
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RAM Addr 57 Mnemonic RINGFRHI Description Ringing Frequency-- High Byte Ringing Frequency-- Low Byte Ringing Waveform dc Offset Ringing Oscillator Initial Phase Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type Init Ex. Hex 3F78 Ex. Dec 20 Unit Hz
RINGFRHI[14:0]
58
RINGFRLO
RINGFRLO[14:3]
Init
6CE8
20
Hz
56
RINGOF
RINGOF[14:0]
Init
0000
0
V
60
RINGPHAS
RINGPHAS[15:3]
Init
0000
Ring Trip Detection 66 RTACDB AC Ring Trip Debounce Interval AC Ring Trip Detect Threshold DC Ring Trip Debounce Interval DC Ring Trip Detect Threshold Ring Trip Low-pass Filter Coeff Period RTACDB[15:0] Init 0003 75 ms
64
RTACTH
RTACTH[15:0]
Init
1086
mA
65
RTDCDB
RTDCDB[15:0]
Init
0003
75
ms
62
RTDCTH
RTDCTH[15:0]
Init
7FFF
mA
63
RTPER
RTPER[15:0]
Init
0028
40
DC Speedup 168 169 SPEEDUP SPEEDUPR DC Speedup Timer Ring Speedup Timer SPEEDUP[15:0] SPEEDUPR[15:0]2 Loop Voltages 13 VBAT Scaled Battery Voltage Measurement Common Mode Voltage Loop Voltage Open Circuit Voltage VOC Delta for Off-Hook VOC Delta Upper Threshold VOC Delta Lower Threshold Battery Tracking Open Circuit Voltage Overhead Voltage Ringing Overhead Voltage Scaled RING Voltage Measurement Scaled TIP Voltage Measurement VBAT[15:0] Diag V Init Init 0000 0000 60 60 ms ms
4 7 0 1 3
VCM VLOOP VOC VOCDELTA VOCHTH
VCM[15:0]2 VLOOP[15:0]2 VOC[15:0]2 VOCDELTA[15:0]2 VOCHTH[15:0]2
Init Diag Init Init Init
0268
3
V V
2668 059A 0198
48 7 2
V V V
2
VOCLTH
VOCLTH[15:0]
Init
F9A2
-8
V
10
VOCTRACK
VOCTRACK[15:0]2
Diag
V
5 6
VOV VOVRING
VOV[15:0]2 VOVRING[14:0]
2
Init Init
0334 0000
4 0
V V
12
VRING
VRING[15:0]
Diag
V
11
VTIP
VTIP[15:0]
Diag
V
Notes: 1. 2.
RAM values are 2's complement unless otherwise noted. Any register not listed is reserved and must not be written. Only positive input values are valid for these RAM addresses.
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8. 16-Bit Control Descriptions
BATHTH: High Battery Switch Threshold (RAM Address 31) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
BATHTH[14:7] R/W
Reset settings = 0x00
Bit Name Function High Battery Switch Threshold. Programs the voltage threshold for selecting the high battery supply (VBATH). Threshold is compared to the RING lead voltage (normal ACTIVE mode) plus the VOV value. 0 to 160.173 V range, 4.907 mV/LSB, 628 mV effective resolution.
14:7
BATHTH[14:7]
BATLPF: Battery Tracking Filter Coefficient (RAM Address 34) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
BATLPF[15:3] R/W
Reset settings = 0x00
Bit Name Function Battery Tracking Filter Coefficient. Programs the digital low-pass filter block that filters the voltage measured on the RING lead when battery tracking is enabled.
15:3
BATLPF[15:3]
BATLTH: Low Battery Switch Threshold (RAM Address 32) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
BATLTH[14:7] R/W
Reset settings = 0x00
Bit Name Function Low Battery Switch Threshold. Programs the voltage threshold for selecting the low battery supply (VBATL). Threshold is compared to the RING lead voltage (normal ACTIVE mode) plus the VOV value. 0 to 160.173 V range, 4.907 mV/LSB, 628 mV effective resolution.
14:7
BATLTH[14:7]
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SI3232
BSWLPF: RING Voltage Filter Coefficient (RAM Address 33) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
BSWLPF[15:3] R/W
Reset settings = 0x00
Bit Name Function RING Voltage Filter Coefficient. Programs the digital low-pass filter block that filters the voltage measured on the RING lead used to determine battery switching threshold.
15:3
BSWLPF[15:3]
CMHITH: Speedup Threshold--High Byte (RAM Address 36) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
CMHITH[15:0] R/W
Reset settings = 0x00
Bit Name Function Speedup Threshold--High Byte. Programs the upper byte of the threshold at which speedup mode in enabled. The CMLOTH RAM location holds the lower byte of this value.
15:0
CMHITH[15:0]
CMLOTH: Speedup Threshold--Low Byte (RAM Address 35) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
CMLOTH[15:0] R/W
Reset settings = 0x00
Bit Name Function Speedup Threshold--Low Byte. Programs the lower byte of the threshold at which speedup mode in enabled. The CMHITH RAM location holds the upper byte of this value.
15:0
CMLOTH[15:0]
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DIAGAC: SLIC Diagnostics AC Output (RAM Address 53) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
DIAGAC[15:0] R/W
Reset settings = 0x00
Bit Name Function SLIC Diagnostic AC Output. Provides a filtered value that reflects the ac rms value from the output of the monitor ADC. The input to the monitor ADC is selected by the setting in the SDIAG register (Register 13). The DIAGACCO RAM location determines the rms filter coefficient used. This register is used for frequencies < 300 Hz.
15:0
DIAGAC[15:0]
DIAGACCO: SLIC Diagnostics AC Filter Coefficient (RAM Address 54) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
DIAGACCO[15:3] R/W
Reset settings = 0x00
Bit Name Function SLIC Diagnostics AC Filter Coefficient. Programs the rms filter coefficient used in the ac measurement result from the monitor ADC.
15:3
DIAGACCO[15:3]
DIAGDC: SLIC Diagnostics dc Output (RAM Address 51) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
DIAGDC[15:0] R/W
Reset settings = 0x00
Bit Name Function SLIC Diagnostic DC Output. Provides a low-pass filtered value that reflects the dc value from the output of the monitor ADC. The input to the monitor ADC is selected by the setting in the SDIAG register (Register 13). The DIAGDCCO RAM location determines the low-pass filter coefficient used.
15:0
DIAGDC[15:0]
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SI3232
DIAGDCCO: SLIC Diagnostics dc Filter Coefficient (RAM Address 52) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
DIAGDCCO[15:3] R/W
Reset settings = 0x00
Bit Name Function SLIC Diagnostics dc Filter Coefficient. Programs the low-pass filter coefficient used in the dc measurement result from the monitor ADC.
15:3
DIAGDCCO[15:3]
DIAGPK: SLIC Diagnostics Peak Detector (RAM Address 55) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
DIAGPK[15:0] R/W
Reset settings = 0x00
Bit Name Function SLIC Diagnostic Peak Detector. Provides filtered value that reflects the peak amplitude from the output of the monitor ADC. The input to the monitor ADC is selected by the setting in the SDIAG register (Register 13).
15:0
DIAGPK[15:0]
ILONG: Longitudinal Current Sense Value (RAM Address 9) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
ILONG[15:0] R/W
Reset settings = 0x00
Bit Name Function Longitudinal Current Sense Value. Holds the realtime measured longitudinal current. 0 to 101.09 mA measurement range, 3.097 A/LSB, 500 A effective resolution. Updated at an 800 Hz rate, signed/magnitude.
15:0
ILONG[15:0]
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Preliminary Rev. 0.96
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ILOOP: Loop Current Sense Value (RAM Address 8) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
ILOOP[15:0] R/W
Reset settings = 0x00
Bit Name Function Loop Current Sense Value. Holds the realtime measured loop current. 0 to 101.09 mA measurement range, 3.097 A/LSB, 500 A effective resolution. 800 Hz update rate, signed/magnitude.
15:0
ILOOP[15:0]
IRING: (Transistor Q5) Current Measurement (RAM Address 18) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
IRING[15:0] R/W
Reset settings = 0x00
Bit Name Function IRING (Transistor Q5) Current Measurement. Reflects the current flowing into the IRING pin of the Si3200 (transistor Q5 of a discrete circuit). 3.097 A/LSB, 2's complement.
15:0
IRING[15:0]
IRINGN: (Transistor Q3) Current Measurement (RAM Address 16) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
IRINGN[15:0] R/W
Reset settings = 0x00
Bit Name Function IRINGN (Transistor Q3) Current Measurement. Reflects the current flowing into the IRINGN pin of the Si3200 (transistor Q3 of a discrete circuit). 195.3 nA/LSB, 2's complement.
15:0
IRINGN[15:0]
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SI3232
IRINGP: (Transistor Q2) Current Measurement (RAM Address 15) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
IRINGP[15:0] R/W
Reset settings = 0x00
Bit Name Function IRINGP (Transistor Q2) Current Measurement. Reflects the current flowing into the IRINGP pin of the Si3200 (transistor Q2 of a discrete circuit). 3.097 A/LSB, 2's complement.
15:0
IRINGP[15:0]
ITIP: (Transistor Q6) Current Measurement (RAM Address 19) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
ITIP[15:0] R/W
Reset settings = 0x00
Bit Name Function ITIP (Transistor Q6) Current Measurement. Reflects the current flowing into the ITIP pin of the Si3200 (transistor Q6 of a discrete circuit). 3.097 A/LSB, 2's complement.
15:0
ITIP[15:0]
ITIPN: (Transistor Q4) Current Measurement (RAM Address 17) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
ITIPN[15:0] R/W
Reset settings = 0x00
Bit Name Function ITIPN (Transistor Q4) Current Measurement. Reflects the current flowing into the ITIPN pin of the Si3200 (transistor Q4 of a discrete circuit). 195.3 nA/LSB, 2's complement.
15:0
ITIPN[15:0]
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Preliminary Rev. 0.96
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ITIPP: (Transistor Q1) Current Measurement (RAM Address 14) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
ITIPP[15:0] R/W
Reset settings = 0x00
Bit Name Function ITIPP (Transistor Q1) Current Measurement. Reflects the current flowing into the ITIPP pin of the Si3200 (transistor Q1 of a discrete circuit). 3.097 A/LSB, 2's complement.
15:0
ITIPP[15:0]
LCRDBI: Loop Closure Detection Debounce Interval (RAM Address 24) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LCRDBI[15:0] R/W
Reset settings = 0x00
Bit Name Function Loop Closure Detection Debounce Interval. Programs the debounce interval during the loop closure detection process. Programmable range is 0 to 40.96 s, 1.25 ms/LSB.
15:0
LCRDBI[15:0]
LCRLPF: Loop Closure Filter Coefficient (RAM Address 25) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LCRLPF[15:3] R/W
Reset settings = 0x00
Bit Name Function Loop Closure Filter Coefficient. Programs the digital low-pass filter block in the loop closure detection circuit. Refer to "4.5.1. Loop Closure Detection" on page 32 for calculation.
15:3
LCRLPF[15:3]
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SI3232
LCRMASK: Loop Closure Mask Interval Coefficient (RAM Address 26) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LCRMASK[15:0] R/W
Reset settings = 0x00
Bit Name Function Loop Closure Mask Interval Coefficient. Programs the loop closure detection mask interval. Programmable range is 0 to 40.96 s, 1.25 s/LSB
15:0
LCRMASK[15:0]
LCRMSKPR: LCR Mask During Polarity Reversal (RAM Address 166) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LCRMSKPR[15:0] R/W
Reset settings = 0x00
Bit Name Function LCR Mask During Polarity Reversal. Programs the loop closure detection mask interval during a polarity reversal. Programmable range is 0 to 40.96 s, 1.25 s/LSB
15:0
LCRMSKPR[15:0]
LCROFFHK: Loop Closure Detection Threshold--On-Hook to Off-Hook Transition (RAM Address 22) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LCROFFHK[15:0] R/W
Reset settings = 0x00
Bit Name Function Loop Closure Detection Threshold--On-Hook to Off-Hook Transition. Programs the loop current threshold at which a valid loop closure is detected when transitioning from on-hook to off-hook. Hysteresis is provided by programming the ONHKTH RAM location to a different value that detects the off-hook to on-hook transition threshold. 0 to 101.09 mA programmable range, 3.097 A/LSB, 396.4 A effective resolution. Usable range is 0 to 61 mA.
15:0
LCROFFHK[15:0]
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SI3232
LCRONHK: Loop Closure Detection Threshold--Off-Hook to On-Hook Transition (RAM Address 23) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LCRONHK[15:0] R/W
Reset settings = 0x00
Bit Name Function Loop Closure Detection Threshold--Off-Hook to On-Hook Transition. Programs the loop current threshold at which a valid loop closure event has been terminated (the off-hook to on-hook transition). The OFFHKTH RAM location determines the loop current threshold for detecting the off-hook to on-hook transition. 0 to 101.09 mA programmable range, 3.097 A/LSB, 396.4 A effective resolution. Usable range is 0 to 61 mA.
15:0
LCRONHK[15:0]
LONGDBI: Ground Key Detection Debounce Interval (RAM Address 29) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LONGDBI[15:0] R/W
Reset settings = 0x00
Bit Name Function Ground Key Detection Debounce Interval. Programs the debounce interval during the ground key detection process. Programmable range is 0 to 40.96 s, 1.25 ms/LSB.
15:0
LONGDBI[15:0]
LONGHITH: Ground Key Detection Threshold (RAM Address 27) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LONGHITH[15:0] R/W
Reset settings = 0x00
Bit 15:0 Name LONGHITH[15:0] Function Ground Key Detection Threshold. Programs the longitudinal current threshold at which a valid ground key event is detected. Hysteresis is provided by programming the LONGLOTH RAM location to a different value that detects the removal of a ground key event. 0 to 101.09 mA programmable range, 3.097 A/LSB, 396.4 A effective resolution. Usable range is 0 to 16 mA.
Preliminary Rev. 0.96
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SI3232
LONGLOTH: Ground Key Removal Detection Threshold (RAM Address 28) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LONGLOTH[15:0] R/W
Reset settings = 0x00
Bit 15:0 Name LONGLOTH[15:0] Function Ground Key Removal Detection Threshold. Programs the longitudinal current threshold at which it is determined that a ground key event has been terminated. 0 to 101.09 mA programmable range, 3.097 A/ LSB, 396.4 A effective resolution. Usable range is 0 to 16 mA.
LONGLPF: Ground Key Filter Coefficient (RAM Address 30) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LONGLPF[15:3] R/W
Reset settings = 0x00
Bit Name Function Ground Key Filter Coefficient. Programs the digital low-pass filter block in the ground key detection circuit. Refer to "4.5.2. Ground Key Detection" on page 34 for calculation.
15:3
LONGLPF[15:3]
PLPF12: Q1/Q2 Thermal Low-pass Filter Coefficient (RAM Address 40) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
PLPF12[15:3] R/W
Reset settings = 0x00
Bit Name Function Q1/Q2 Thermal Low-pass Filter Coefficient. Programs the thermal low-pass filter value used to calculate the power in transistors Q1 and Q2. Also used to set thermal IPF when using Si3200. Refer to "4.4.6. Power Filter and Alarms" on page 27 for use.
15:3
PLPF12[15:3]
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PLPF34: Q3/Q4 Thermal Low-pass Filter Coefficient (RAM Address 41) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
PLPF34[15:3] R/W
Reset settings = 0x00
Bit Name Function Q3/Q4 Thermal Low-pass Filter Coefficient. Programs the thermal low-pass filter value used to calculate the power in transistors Q3 and Q4. Refer to "4.4.6. Power Filter and Alarms" on page 27 for use.
15:3
PLPF34[15:3]
PLPF56: Q5/Q6 Thermal Low-pass Filter Coefficient (RAM Address 42) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
PLPF56[15:3] R/W
Reset settings = 0x00
Bit Name Function Q5/Q6 Thermal Low-pass Filter Coefficient. Programs the thermal low-pass filter value used to calculate the power in transistors Q5 and Q6. Refer to "4.4.6. Power Filter and Alarms" on page 27 for use.
15:3
PLPF56[15:3]
PMAMPL: Pulse Metering Amplitude (RAM Address 68) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
PMAMPL[15:0] R/W
Reset settings = 0x00
Bit Name Function Pulse Metering Amplitude. Programs the voltage amplitude of the pulse metering signal. Refer to "4.13.2. Pulse Metering Generation" on page 46 for use.
15:0
PMAMPL[15:0]
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SI3232
PMAMPTH: Pulse Metering AGC Amplitude Threshold (RAM Address 70) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
PMAMPTH[15:0] R/W
Reset settings = 0x00
Bit Name Function Pulse Metering AGC Amplitude Threshold. Programs the voltage threshold for the automatic gain control (AGC) stage in the transmit audio path. Refer to "4.13.2. Pulse Metering Generation" on page 46 for use.
15:0
PMAMPTH[15:0]
PMFREQ: Pulse Metering Frequency (RAM Address 67) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
PMFREQ[15:3] R/W
Reset settings = 0x00
Bit Name Function Pulse Metering Frequency. Programs the frequency of the pulse metering signal. Refer to "4.13.2. Pulse Metering Generation" on page 46 for use.
15:3
PMFREQ[15:3]
PMRAMP: Pulse Metering Ramp Rate (RAM Address 69) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
PMRAMP[15:0] R/W
Reset settings = 0x00
Bit Name Function Pulse Metering Ramp Rate. Programs the attack and decay rate of the pulse metering signal. Programmable range is 0 to 4.0965 at 0.125 ms/LSB (15 bit). Refer to "4.13.2. Pulse Metering Generation" on page 46 for use.
15:0
PMRAMP[15:0]
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PQ1DH: Q1 Calculated Power (RAM Address 44) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
PQ1DH[15:0] R/W
Reset settings = 0x00
Bit Name Function Q1 Calculated Power. Provides the calculated power in transistor Q1 when used with discrete linefeed circuitry. 0 to 16.319 W range, 498 W/LSB.
15:0
PQ1DH[15:0]
PQ2DH: Q2 Calculated Power (RAM Address 45) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
PQ2DH[15:0] R/W
Reset settings = 0x00
Bit Name Function Q2 Calculated Power. Provides the calculated power in transistor Q2. Used with discrete linefeed circuitry. 0 to 16.319 W range, 498 W/LSB.
15:0
PQ2DH[15:0]
PQ3DH: Q3 Calculated Power (RAM Address 46) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
PQ3DH[15:0] R/W
Reset settings = 0x00
Bit Name Function Q3 Calculated Power. Provides the calculated power in transistor Q3. Used with discrete linefeed circuitry. 0 to 1.03 W range, 31.4 W/LSB.
15:0
PQ3DH[15:0]
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SI3232
PQ4DH: Q4 Calculated Power (RAM Address 47) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
PQ4DH[15:0] R/W
Reset settings = 0x00
Bit Name Function Q4 Calculated Power. Provides the calculated power in transistor Q4. Used with discrete linefeed circuitry. 0 to 1.03 W range, 31.4 W/LSB.
15:0
PQ4DH[15:0]
PQ5DH: Q5 Calculated Power (RAM Address 48) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
PQ5DH[15:0] R/W
Reset settings = 0x00
Bit Name Function Q5 Calculated Power. Provides the calculated power in transistor Q5. Used with discrete linefeed circuitry. 0 to 16.319 W range, 498 W/LSB.
15:0
PQ5DH[15:0]
PQ6DH: Q6 Calculated Power (RAM Address 49) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
PQ6DH[15:0] R/W
Reset settings = 0x00
Bit Name Function Q6 Calculated Power. Provides the calculated power in transistor Q6. Used with discrete linefeed circuitry. 0 to 16.319 W range, 498 W/LSB.
15:0
PQ6DH[15:0]
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PSUM: Total Calculated Power (RAM Address 50) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
PSUM[15:0] R/W
Reset settings = 0x00
Bit Name Function Total Calculated Power. Provides the total calculated power in transistors Q1 through Q6. Using the Si3200, this RAM location reflects the total power dissipated in the Si3200 package. 0 to 34.72 W range, 1059.6 W/LSB
15:0
PSUM[15:0]
PTH12: Q1/Q2 Power Alarm Threshold (RAM Address 37) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
PTH12[15:0] R/W
Reset settings = 0x00
Bit Name Function Q1/Q2 Power Alarm Threshold. Programs the power threshold in transistors Q1 and Q2 at which a power alarm is triggered. Also programs the total power threshold when using Si3200. 0 to 16.319 W programmable range, 498 W/LSB (0 to 34.72 W range, 1059.6 W/LSB in Si3200 mode). Refer to "4.4.6. Power Filter and Alarms" on page 27 for use.
15:0
PTH12[15:0]
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SI3232
PTH34: Q3/Q4 Power Alarm Threshold (RAM Address 38) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
PTH34[15:0] R/W
Reset settings = 0x00
Bit Name Function Q3/Q4 Power Alarm Threshold. Programs the power threshold in transistors Q3 and Q4 at which a power alarm is triggered. 0 to 1.03 W programmable range, 31.4 W/LSB. Refer to "4.4.6. Power Filter and Alarms" on page 27 for use.
15:0
PTH34[15:0]
PTH56: Q5/Q6 Power Alarm Threshold (RAM Address 39) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
PTH56[15:0] R/W
Reset settings = 0x00
Bit Name Function Q5/Q6 Power Alarm Threshold. Programs the power threshold in transistors Q5 and Q6 at which a power alarm is triggered. 0 to 16.319 W programmable range, 498 W/LSB. Refer to "4.4.6. Power Filter and Alarms" on page 27 for use.
15:0
PTH56[15:0]
RB56: Q5/Q6 Base Resistance (RAM Address 43) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
RB56[15:0] R/W
Reset settings = 0x00
Bit Name Function Q5/Q6 Base Resistance. Programs the base resistance feeding transistors, Q5 and Q6.
15:0
RB56[15:0]
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RINGAMP: Ringing Amplitude (RAM Address 59) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
RINGAMP[15:0] R/W
Reset settings = 0x00
Bit Name Function Ringing Amplitude. This RAM location programs the peak ringing amplitude. Refer to "4.6. Ringing Generation" on page 37 for use.
15:0
RINGAMP[15:0]
Reset settings = 0x00
RINGFRHI: Ringing Frequency High Byte (RAM Address 57) Bit Name Type Bit Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
RINGFRHI[14:0] R/W
Function Ringing Frequency High Byte. This RAM location programs the upper byte of the ringing frequency coefficient. The RINGFRLO RAM location holds the lower byte. Refer to "4.6. Ringing Generation" on page 37 for use.
14:0
RINGFRHI[14:0]
RINGFRLO: Ringing Frequency Low Byte (RAM Address 58) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
RINGFRLO[15:3] R/W
Reset settings = 0x00
Bit Name Function Ringing Frequency Low Byte. This RAM location programs the lower byte of the ringing frequency coefficient. The RINGFRHI RAM location holds the upper byte. Refer to "4.6. Ringing Generation" on page 37 for use.
15:3
RINGFRLO[15:3]
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RINGOF: Ringing Waveform dc Offset (RAM Address 56) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
RINGOF[14:0] R/W
Reset settings = 0x00
Bit Name Function Ringing Waveform dc Offset. Programs the amount of dc offset that is added to the ringing waveform during ringing mode. 0 to 63.3 V programmable range, 4.907 mV/LSB, 1.005 V effective resolution.
14:0
RINGOF[14:0]
RINGPHAS: Ringing Oscillator Initial Phase (RAM Address 60) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
RINGPHAS[15:3] R/W
Reset settings = 0x00
Bit Name Function RInging Oscillator Initial Phase. Programs the initial phase of the ringing oscillator. 0 to 1.024 s range, 31.25 s/LSB for trapezoidal ringing.
15:3
RINGPHAS[15:3]
RTACDB: AC Ring Trip Debounce Interval (RAM Address 66) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
RTACDB[15:0] R/W
Reset settings = 0x00
Bit Name Function AC Ring Trip Debounce Interval. Programs the debounce interval for the ac loop current detection circuit. Refer to "4.8. Ring Trip Detection" on page 41 for recommended values.
15:0
RTACDB[15:0]
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RTACTH: AC Ring Trip Detect Threshold (RAM Address 64) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
RTACTH[15:0] R/W
Reset settings = 0x00
Bit Name Function AC Ring Trip Detect Threshold. Programs the ac loop current threshold value above which a valid ring trip event is detected. See "4.8. Ring Trip Detection" on page 41 for recommended values.
15:0
RTACTH[15:0]
RTDCDB: DC Ring Trip Debounce Interval (RAM Address 65) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
RTDCDB[15:0] R/W
Function DC Ring Trip Debounce Interval. Programs the debounce interval for the dc loop current detection circuit. 0 to 40.96 s programmable range, 1.25 s/LSB. Refer to "4.8. Ring Trip Detection" on page 41 for recommended values.
Reset settings = 0x00 Bit Name 15:0 RTDCDB[15:0]
RTDCTH: DC Ring Trip Detect Threshold (RAM Address 62) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
RTDCTH[15:0] R/W
Reset settings = 0x00
Bit Name Function DC Ring Trip Detect Threshold. Programs the dc loop current threshold value above which a valid ring trip event is detected. See "4.8. Ring Trip Detection" for recommended values.
15:0
RTDCTH[15:0]
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SI3232
RTPER: Ring Trip Low-pass Filter Coefficient (RAM Address 63) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
RTPER[15:0] R/W
Reset settings = 0x00
Bit Name Function Ring Trip Low-pass Filter Coefficient. Programs the low-pass filter coefficient used in the ring trip detection circuit. See "4.8. Ring Trip Detection" for recommended values.
15:0
RTPER[15:0]
SPEEDUP: DC Settling Speedup Timer (RAM Address 168) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SPEEDUP[15:0] R/W
Reset settings = 0x00
Bit Name Function DC Settling Speedup Timer. Programs the dc speedup timer that allows quicker settling during loop transitions. This timer is invoked by the common-mode threshold detectors, CMHITH and CMLOTH. 1.25 ms/LSB, exception: 0x0000 = 60 ms (default).
15:0
SPEEDUP[15:0]
SPEEDUPR: Ringing Speedup Timer (RAM Address 169) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SPEEDUPR[15:0] R/W
Reset settings = 0x00
Bit Name Function Ringing Speedup Timer. Programs the dc speedup timer that allows quicker settling following ringing bursts. This timer is invoked by any mode change from the ringing state. 40.96 s range, 1.25 ms/LSB, exception: 0x0000 = 60 ms (default).
15:0
SPEEDUPR[15:0]
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VBAT: Scaled Battery Voltage Measurement (RAM Address 13) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
VBAT[15:0] R/W
Reset settings = 0x00
Bit Name Function Scaled Battery Voltage Measurement. Reflects the battery voltage measured through the monitor ADC. 0 to 160.173 V range, 4.907 mV/LSB, 628 mV effective resolution. (251 mV effective resolution for VBAT < 64.07 V).
15:0
VBAT[15:0]
VCM: Common Mode Voltage (RAM Address 4) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
VCM[14:0] R/W
Reset settings = 0x00
Bit Name Function Common Mode Voltage. Programs the common mode voltage between the TIP lead and ground in normal polarity (between RING and ground in reverse polarity). The recommended value is 3 V, but can be programmed between 0 and 63.3 V. 4.907 mV/LSB, 1.005 V effective resolution,
14:0
VCM[14:0]
VLOOP: Loop Voltage Sense Value (RAM Address 7) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
VLOOP[15:0] R/W
Reset settings = 0x00
Bit Name Function Loop Voltage Sense Value. Holds the realtime measured loop voltage across TIP-RING. 0 to 160.173 V range, 4.907 mV/LSB, 628 mV effective resolution (251 mV effective resolution for VLOOP < 64.07 V.
15:0
VLOOP[15:0]
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SI3232
VOC: Open Circuit Voltage (RAM Address 0) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
VOC[14:0] R/W
Reset settings = 0x00
Bit Name Function Open Circuit Voltage. Programs the TIP-RING voltage during on-hook conditions. The recommended value is 48 V but can be programmed between 0 and 63.3 V. 4.907 mV/LSB, 1.005 V effective resolution.
14:0
VOC[14:0]
VOCDELTA: Open Circuit Off-Hook Offset Voltage (RAM Address 1) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
VOCDELTA[14:0] R/W
Reset settings = 0x00
Bit Name Function
14:0 VOCDELTA[14:0] Open Circuit Off-Hook Offset Voltage. Programs the amount of offset that is added to the VOC RAM value when the device transitions to off-hook. The recommended value is 7 V. 0 to 63.3 V range, 4.907 mV/ LSB, 1.005 V effective resolution.
VOCHTH: VOC Delta Upper Threshold (RAM Address 3) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
VOCHTH[15:0] R/W
Reset settings = 0x00
Bit Name Function VOC Delta Upper Threshold.
15:0
VOCHTH[15:0]
Programs the voltage delta above the VOC value at which the VOCDELTA offset voltage is removed. This threshold is only applicable during the off-hook to on-hook transition, and the VOCTHDL RAM location determines the threshold voltage during the onhook to off-hook transition. Default value is 2 V. 0 to 63.3 V range, 4.907 mV/LSB, 1.005 V effective resolution.
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VOCLTH: VOC Delta Lower Threshold (RAM Address 2) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
VOCLTH[15:0] R/W
Reset settings = 0x00
Bit Name Function VOC Delta Lower Threshold.
15:0
VOCLTH[15:0]
Programs the voltage delta below the VOC value at which the VOCDELTA offset voltage is added. This threshold is only applicable during the on-hook to off-hook transition, and the VOCTHDH RAM location determines the threshold voltage during the off-hook to on-hook transition. Default value is -8 V. 0 to 63.3 V range, 4.907 mV/LSB, 1.005 V effective resolution.
VOCTRACK: Battery Tracking Open Circuit Voltage (RAM Address 10) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
VOCTRACK[15:0] R/W
Reset settings = 0x00
Bit Name Function 15:0 VOCTRACK[15:0] Battery Tracking Open Circuit Voltage. Reflects the TIP-RING voltage during on-hook conditions when the battery supply has dropped below the point where the VOC setting cannot be maintained. 0 to 63.3 V programmable range, 4.907 mV/LSB, 1.005 V effective resolution.
VOV: Overhead Voltage (RAM Address 5) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
VOV[14:0] R/W
Reset settings = 0x00
Bit 14:0 Name VOV[14:0] Function Overhead Voltage. Programs the overhead voltage between the RING lead and the voltage on the VBAT pin in normal polarity (between TIP and ground in reverse polarity). This value increases or decreases as the battery voltage changes to maintain a constant open circuit voltage, but maintains its user-defined setting to ensure sufficient overhead for audio transmission when the battery voltage decreases. 0 to 63.3 V programmable range, 4.907 mV/ LSB, 1.005 V effective resolution.
Preliminary Rev. 0.96
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SI3232
VOVRING: Ringing Overhead Voltage (RAM Address 6) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
VOVRING[14:0] R/W
Reset settings = 0x00
Bit Name Function
14:0
VOVRING[14:0] Ringing Overhead Voltage. Programs the overhead voltage between the peak negative ringing level and VBATH. This value increases or decreases as the battery voltage changes in order to maintain a constant open circuit voltage but maintains its user-defined setting to ensure sufficient overhead for audio transmission when the battery voltage decreases. 0 to 63.3 V programmable range, 4.907 mV/LSB, 1.005 V effective resolution.
VRING: Scaled RING Voltage Measurement (RAM Address 12) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
VRING[15:0] R/W
Reset settings = 0x00
Bit Name Function Scaled RING Voltage Measurement. Reflects the RING-to-ground voltage measured through the monitor ADC. 0 to 160.173 V range, 4.907 mV/LSB, 628 mV effective resolution (251 mV effective resolution for VRING < 64.07 V). Updated at 800 Hz rate, 2's complement.
15:0
VRING[15:0]
VTIP: Scaled TIP Voltage Measurement (RAM Address 11) Bit Name Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
VTIP[15:0] R/W
Reset settings = 0x00
Bit Name Function Scaled TIP Voltage Measurement. Reflects the TIP to ground voltage measured through the monitor ADC. 4.92 mV/LSB, 2's complement. 0 to 160.173 V range, 4.907 mV/LSB, 628 mV effective resolution (251 mV effective resolution for VTIP < 64.07 V). Updated at 800 Hz rate, 2's complement.
15:0
VTIP[15:0]
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9. Pin Descriptions: SI3232
SRINGDCa
SRINGACa
SVBATa RPOa RPIa RNIa RNOa CAPPa CAPMa QGND IREF CAPMb CAPPb RNOb RNIb RPIb RPOb SVBATb
1 2 3 4 5 6 7 8 9
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44
BATSELa
STIPDCa
STIPACa
THERMa
IRINGNa
IRINGPa
VRXNa
VRXPa
VTXNa
VTXPa
ITIPNa
ITIPPa
GND1
VDD1
GPOa CS SDITHRU SDI SDO SCLK VDD4 GND4 INT PCLK GND3 VDD3 GPOb BATSELb FSYNC RESET
10 11 12 13 14 15
SI3232 64-Lead TQFP (epad)
43 42 41 40 39 38 37 36 35 34
16 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 THERMb SRINGDCb ITIPNb ITIPPb IRINGPb VCM STIPACb VTXPb STIPDCb SRINGACb IRINGNb VRXPb VRXNb VTXNb GND2 VDD2
Pin #(s)
Symbol
Input/ Description Output
1, 16 2, 15 3, 14 4, 13 5, 12 6, 11 7, 10 8 9
SVBATa, SVBATb RPOa, RPOb RPIa, RPIb RNIa, RNIb RNOa, RNOb CAPPa, CAPPb CAPMa, CAPMb QGND IREF
I O I I O
Battery Sensing Input--Analog current input used to sense battery voltage. Transconductance Amplifier Resistor Input Connection. Transconductance Amplifier Resistor Output Connection. Transconductance Amplifier Resistor Output Connection. Transconductance Amplifier Resistor Input Connection. Differential Capacitor--Capacitor used in low-pass filter to stabilize SLIC feedback loops. Common Mode Capacitor--Capacitor used in low-pass filter to stabilize SLIC feedback loops. Component Reference Ground--Return path for differential and common-mode capacitors. Do not connect to system ground.
I
IREF Current Reference--Connects to an external resistor used to provide a high-accuracy reference current. Return path for IREF resistor. Should be routed to QGND pin. TIP Sense--Analog current input used to sense dc voltage on TIP side of subscriber loop. TIP Transmit Input--Analog input used to sense ac voltage on TIP side of subscriber loop.
17, 64 18, 63
STIPDCb, STIPDCa STIPACb, STIPACa
I I
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Pin #(s) Symbol Input/ Description Output
19, 62 20, 61 21, 60 22, 59 23, 58
SRINGACb, SRINGACa SRINGDCb, SRINGDCa ITIPNb, ITIPNa IRINGNb, IRINGNa ITIPPb, ITIPPa
I I O O O
RING Transmit Input--Analog input used to sense ac voltage on RING side of subscriber loop. RING Sense--Analog current input used to sense dc voltage on RING side of subscriber loop. Negative TIP Current Control--Analog current output providing dc current return path to VBAT from TIP side of the loop. Negative RING Current Control--Analog current output providing dc current return path to VBAT from RING side of loop. Positive TIP Current Control--Analog current output driving dc current onto TIP side of subscriber loop in normal polarity. Also modulates ac current onto TIP side of loop. Supply Voltage--Power supply for internal analog and digital circuitry. Connect all VDD pins to the same supply and decouple to adjacent GND pins as close to the pins as possible. Ground--Ground connection for internal analog and digital circuitry. Connect all pins to low-impedance ground plane.
24, 37, 42, 57 25, 38, 41, 56 26, 55
VDD2, VDD3, VDD4, VDD1 GND2, GND3 GND4, GND1 IRINGPb, IRINGPa O
Positive RING Current Control--Analog current output driving dc current onto RING side of subscriber loop in reverse polarity. Also modulates ac current onto RING side of loop. Temperature Sensor--Used to sense the internal temperature of the Si3200. Connect to THERM pin of Si3200 or to VDD when using discrete linefeed circuit. Common Mode Voltage Input--Connect to external common mode voltage source. Differential Analog Receive Input for SLIC Channel b. Differential Analog Transmit Output for SLIC Channel b. Reset--Active low. Hardware reset used to place all control registers in known state. An internal pulldown resistor asserts this pin low when it is not driven externally. Frame Sync--8 kHz frame synchronization signal for internal timing. May be short or long pulse format. Battery Voltage Select Pin--Used to switch between high and low external battery supplies. General Purpose Driver Output--Used to drive test relays for connecting loop test equipment or as a second battery select pin. PCM System Clock--Master clock input. Interrupt--Maskable interrupt output. Open drain output for wireORed operation. Serial Port Bit Clock Input--Controls serial data on SDO and latches data on SDI. Serial Port Data Out--Serial port control data output. Serial Port Data In--Serial port control data input.
27, 54
THERMb, THERMa
I
28 29, 30 31, 32 33
VCM VRXPb, VRXNb VTXPb, VTXNb RESET
I I O I
34 35, 49 36, 48 39 40 43 44 45
FSYNC BATSELb, BATSELa GPOb, GPOa PCLK INT SCLK SDO SDI
I O O I O I O I
118
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Pin #(s) Symbol Input/ Description Output
46
SDITHRU
O
Serial Daisy Chain--Enables up to 16 devices to use a single CS for serial port control. Connect SDITHRU pin from master device to SDI pin of slave device. An internal pullup resistor holds this pin high during idle periods. Chip Select--Active low. When inactive, SCLK and SDIO are ignored. When active, serial port is operational. Differential Analog Transmit Output for SLIC Channel a. Differential Analog Receive Input for SLIC Channel a. Exposed Die Paddle Ground. Connect to a low-impedance ground plane via topside PCB pad directly under the part. See "12. Package Outline: 64-Pin eTQFP" on page 123 for PCB pad dimensions.
47 50, 51 52, 53 epad
CS VTXNa, VTXPa VRXNa, VRXPa GND
I O I
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SI3232
10. Pin Descriptions: Si3200
Si3200 16-Lead SOIC (epad)
TIP NC RING VBAT VBATH VBATL GND VDD 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ITIPP ITIPN THERM IRINGP IRINGN NC NC BATSEL
Pin #(s)
Symbol
Input/ Output
Description TIP Output--Connect to the TIP lead of the subscriber loop. No Internal Connection--Do not connect to any electrical signal.
1 2 3 4
TIP NC RING VBAT
I/O
I/O
RING Output--Connect to the RING lead of the subscriber loop. Operating Battery Voltage--Si3200 internal system battery supply. Connect SVBATa/b pin from SI3232 and decouple with a 0.1 F/100 V filter capacitor. High Battery Voltage--Connect to the system ringing battery supply. Decouple with a 0.1 F/100 V filter capacitor.
5 6
VBATH VBATL --
Low Battery Voltage--Connect to lowest system battery for off-hook operation driving short loops. An internal diode prevents leakage current when operating from VBATH. Ground--Connect to a low-impedance ground plane. Supply Voltage--Main power supply for all internal circuitry. Connect to a 3.3 V or 5 V supply. Decouple locally with a 0.1 F/10 V capacitor.
7 8 9 10 11 12 13 14
GND VDD BATSEL NC NC IRINGN IRINGP THERM I I O I
Battery Voltage Select--Connect to the BATSEL pin of the SI3232 through an external resistor to enable automatic battery switching. No Internal Connection--Do not connect to any electrical signal. No Internal Connection--Do not connect to any electrical signal. Negative RING Current Control--Connect to the IRINGN lead of the SI3232. Positive RING Current Drive--Connect to the IRINGP lead of the SI3232. Thermal Sensor--Connection to internal temperature-sensing circuit. Connect to THERM pin of SI3232.
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Pin #(s) Symbol Input/ Output Description Negative TIP Current Control--Connect to the ITIPN lead of the SI3232. Positive TIP Current Control--Connect to the ITIPP lead of the SI3232. Exposed Die Paddle Ground. For adequate thermal management, the exposed die paddle should be soldered to a PCB pad that is connected to low-impedance inner and/or backside ground planes using multiple vias. See "13. Package Outline: 16-Pin ESOIC" on page 124 for PCB pad dimensions.
15 16 epad
ITIPN ITIPP GND
I I
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SI3232
11. Ordering Guide
Part Number
Package
Lead Free
Temp Range
SI3232-X-FQ SI3232-X-GQ Si3200-X-FS Si3200-X-GS Si3200-KS Si3200-BS
TQFP-64 TQFP-64 SOIC-16 SOIC-16 SOIC-16 SOIC-16
Yes Yes Yes Yes No No
0 to 70 C -40 to 85 C 0 to 70 C -40 to 85 C 0 to 70 C -40 to 85 C
Notes: 1. Add an "R" at the end of the device to denote tape and reel option; 2500 quantity per reel. 2. "X" denotes product revision.
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12. Package Outline: 64-Pin eTQFP
Figure 39 illustrates the package details for the SI3232. Table 33 lists the values for the dimensions shown in the illustration.
Figure 39. 64-Pin Thin Quad Flat Package (TQFP) Table 33. 64-Pin Package Diagram Dimensions
Symbol Min Millimeters Nom Max Symbol Min Millimeters Nom Max
A A1 A2 b c D D1 D2 e
-- 0.05 0.95 0.17 0.09
-- -- 1.00 0.22 -- 12.00 BSC. 10.00 BSC. 4.50 0.50 BSC.
1.20 0.15 1.05 0.27 0.20
E E1 E2 L aaa bbb ccc ddd
4.35 0.45 -- -- -- -- 0
12.00 BSC. 10.00 BSC. 4.50 0.60 -- -- -- -- 3.5
4.65 0.75 0.20 0.20 0.08 0.08 7
4.35
4.65
Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1982. 3. This package outline conforms to JEDEC MS-026, variant ACD-HD. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020B specification for Small Body Components.
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SI3232
13. Package Outline: 16-Pin ESOIC
Figure 40 illustrates the package details for the Si3201. Table 34 lists the values for the dimensions shown in the illustration.
16
9 h E H -B- .25 M B M x45
1
B
8
Bottom Side Exposed Pad 2.3 x 3.6 mm
L Detail F
.25 M C A M B S
-A-
D C -C- A See Detail F
e
A1
Seating Plane
Weight: Approximate device weight is 0.15 grams.
Figure 40. 16-Pin Thermal Enhanced Small Outline Integrated Circuit (ESOIC) Package
Table 34. Package Diagram Dimensions
Millimeters Symbol Min Max
A A1 B C D E e H h L

1.35 0 .33 .19 9.80 3.80 5.80 .25 .40 -- 0
1.75 0.15 .51 .25 10.00 4.00 6.20 .50 1.27 0.10 8
1.27 BSC
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SUPPORT DOCUMENTATION
AN55: Dual ProSLIC User Guide AN63: Si322x Coefficient Generator User's Guide AN64: Dual ProSLIC LINC User Guide AN68: 8-Bit Microcontroller Board Hardware Reference Guide AN71: Si3220/Si3225 GR-909 testing AN74: SiLINKPS-EVB User's Guide AN86: Ringing/Ringtrip Operation and Architecture on the Si3220/Si3225 SI3232PPT0-EVB Data Sheet
Note: Refer to www.silabs.com for a current list of support documents for this chipset.
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SI3232
DOCUMENT CHANGE LIST
Revision 0.95 to Revision 0.96
The following changes are specific to Rev G of the SI3232 silicon: "4.5.2. Ground Key Detection" on page 34
Added descriptive text and ILONG equation.
Register , "ID: Chip Identification (Register Address 0)," on page 67
Added register value for Silicon Rev. G.
The following changes are corrections to Rev 0.96. Table 34 on page 124. Corrected 16-pin ESOIC dimension A1. "4.5.1. Loop Closure Detection" on page 32
Added descriptive text and ILOOP equation.
"4.16. SPI Control Interface" on page 50
Added pulldown resistor description
Added description for current limiting resistors on VBATH and VDD connected to the Si3200 on page 19. Revised "2. Typical Application Schematic" on page 17.
Added pulldown resistor to SDO pin. Added R20-R23, C23, C24, C32, and C33 to VBATH and VDD of Si3200.
Updated "11. Ordering Guide" on page 122. Updated 64-pin eTQFP drawing on page 123.
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NOTES:
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SI3232
CONTACT INFORMATION
Silicon Laboratories Inc.
4635 Boston Lane Austin, TX 78735 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: ProSLICinfo@silabs.com Internet: www.silabs.com
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories, Silicon Labs, and ProSLIC are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
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